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Jobs · Quality Assurance · California

Principal Validation Engineer

Microsoft · Mountain View, CA · 2 wk ago
HybridQuality Assurance$143k–$275k/yrFull-time

We are seeking a Principal Validation Engineer to join the Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. In this role, you will play a key role in silicon bring-up, electrical and functional validation, and lab infrastructure development for next-generation AI silicon.

About the role

You will work across silicon validation, board design, electrical engineering, FPGA prototyping, and system integration, enabling successful execution from first silicon through product readiness. The ideal candidate combines strong post-silicon validation experience with hands-on expertise in hardware platforms, electrical engineering, board-level debug, and lab operations.

Responsibilities

  • Silicon bring-up and validation of complex AI SoCs, FPGA prototypes, and hardware platforms.
  • Drive board-level debug and root-cause analysis across silicon, firmware, power delivery, clocks, resets, and high-speed interfaces.
  • Partner with PCB, Package, Power, Mechanical, Signal Integrity, Design, Verification, and Architecture teams to develop and validate hardware platforms.
  • Review schematics, PCB layouts, power architecture, and board designs to ensure robust validation and bring-up readiness.
  • Define and execute electrical characterization plans including power, thermal, margining, and high-speed interface validation.
  • Develop validation strategies, test plans, firmware, and automation infrastructure for pre-silicon and post-silicon environments.
  • Architect, deploy, and maintain validation labs including rack infrastructure, FPGA platforms, automation frameworks, and lab instrumentation.
  • Utilize lab equipment including oscilloscopes, logic analyzers, protocol analyzers, waveform generators, power analyzers, and environmental systems to debug complex hardware and system issues.
  • Drive system integration and debug across PCIe, Ethernet, DDR/HBM, JTAG, I2C, SPI, UART, and other platform interfaces.
  • Collaborate with cross-functional teams to influence next-generation silicon, board, and platform designs.
  • Improve validation efficiency through innovative debug methodologies, automation, and lab workflows.
  • Mentor engineers in hardware bring-up, lab debugging, electrical engineering fundamentals, and validation methodologies.

Requirements

  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • OR equivalent experience.
  • Ability to meet Microsoft, customer and/or government security screening requirements, including Microsoft Cloud Background Check every two years.
  • This role requires access to export-controlled information; proof of citizenship, U.S. residency, or protected status may be required.

Preferred Qualifications

  • 10+ years of related technical engineering experience
  • OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience or internship experience
  • OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 10+ years of experience in pre-silicon and post-silicon validation with a proven track record of delivering high-performance CPUs, vector processors, or GPUs.
  • Experience leading validation lab planning, deployment, operation, and scaling activities.
  • Experience with PCB design flows, schematic capture, signal integrity, power integrity, and board manufacturing processes.
  • Experience supporting multiple silicon product cycles from platform definition through production.
  • Understanding of power delivery networks, voltage regulators, clocking architectures, and thermal systems.
  • Experience driving cross-functional execution with EE, ME, firmware, design, architecture, and validation teams.
  • Excellent communication, leadership, and problem-solving skills.

Pay

The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. For specific work locations within the San Francisco Bay area and New York City metropolitan area, the base pay range is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation.

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