Principal System Power Management and Performance Architect

About the role

NVIDIA builds the silicon behind AI, accelerated computing, and graphics. Every watt of performance and every degree of thermal headroom traces back to decisions made in power, performance, and thermal architecture. We are the Silicon Co-Design Group (SCG). We identify, own, and drive system-level co-design ideas. We start with initial concepts and advance to product differentiation across NVIDIA's roadmap.

Responsibilities

• Define the multi-generation roadmap for system-level power and performance features, grounded in prototyping, use-case analysis, and cost/benefit trade-offs across segments.
• Own the architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features.
• Lead system-level boot and IST architecture defining how power and clock domains initialize, sequence, and recover across complex multi-IP systems where the interaction space is large and the failure modes matter.
• Drive power management strategy at datacenter scale, including rack-level power telemetry and platform state coordination in high-performance environments.
• Identify and redesign system-level processes that break under new product requirements—boot/reset flows, low-power entry/exit sequences, and control-system policies across IPs.
• Serve as the multi-functional technical authority across architecture, ASIC, board/platform, and firmware teams. You improve the power-performance trade-offs by influencing decisions made by teams you do not control.

Requirements

• BS or MS in EE/CE, or equivalent experience proven through the work itself
• 15+ years of system architecture, development, and validation experience with a strong focus on power and performance-per-watt optimization in datacenter or high-performance platforms.
• A verifiable history of guiding architecture decisions that shipped across multiple silicon programs.
• Extensive knowledge of HSIO power management, DVFS, P-states, system boot flows, and low-power entry/exit architecture, including how they interact with IP, firmware, and platform layers.

Qualifications

• Strong fundamentals in low-power design, power management techniques, and rack-level performance architecture.
• Practical, hands-on depth in at least two of the following: system power management, robust boot flow optimizations, HSIO, and memory power management.
• A power management architecture or methodology you introduced that survived multiple silicon generations and was adopted beyond your immediate team.
• A demonstrated AI/agentic workflow practice: Not just tool use, but a disciplined approach to compressing engineering velocity with AI while applying strong judgment to validate and refine results.
• Visible technical leadership through patents, publications, conference presentations, standards participation, or broader industry recognition for work that influenced products, roadmaps, or engineering practice.

Skills

• Ability to carry ambiguous product-level power and performance problems from concept through silicon correlation to release trade-off.
• Proven ability to influence decisions made by teams you do not control.

Benefits

• Comprehensive benefits package
• Widely considered to be one of the technology world’s most desirable employers

Pay

• Base salary range: 232,000 USD - 368,000 USD

Schedule

• Full time