Principal/ Sr. Principal FPGA Design Engineer

Relocation assistance may be available. Must be a US Citizen with ability to obtain and maintain Top Secret security clearance with SCI.

About the role

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history. Our team is chartered with providing the skills and innovative technologies to develop, design, produce, and sustain optimized product lines across the sector while providing a decisive advantage to the warfighter.

We are seeking a talented FPGA Design engineer with signal processing experience to join our growing team in Rolling Meadows, IL. As an FPGA Design Engineer, you will join our diverse team and be responsible for research, requirements analysis and systems architecture, design, coding, test bench design, verification, synthesis, and place & route for our digital signal processing products. You will work with digital subsystem and circuit card designs utilizing the latest FPGA technologies from major vendors (Xilinx, Intel/Altera, Microsemi/Actel) and support high-speed interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing, and processor interfaces.

Responsibilities

• Design, code, and verify FPGA-based solutions using VHDL and/or Verilog
• Develop and optimize digital signal processing algorithms on FPGAs
• Perform requirements analysis and systems architecture for FPGA designs
• Create and maintain test benches for verification
• Achieve timing closure on dense FPGA designs
• Conduct synthesis, place & route, static timing analysis, and power analysis
• Work with high-speed interfaces (e.g., AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet)
• Collaborate with cross-functional teams to debug and prototype designs
• Utilize FPGA simulation tools to verify performance of complex RTL blocks
• Develop FPGA/SW interfaces and controls
• Support hardware-level debugging using tools such as Signal Generators, Logic Analyzers, Digital Oscilloscopes, and Embedded FPGAs

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a similar discipline
• In-depth knowledge of VHDL and/or Verilog
• Proficiency in High-Level Synthesis (Xilinx Vivado HLS and/or Mentor Catapult HLS) with C++
• Expertise achieving timing closure on dense FPGA designs
• Working knowledge of DSP structures and techniques
• Proficiency in Python, C, or other scripting languages
• Extensive experience generating test benches
• Experience with FPGA design flow, including RTL/gate-level simulation, synthesis, place and route, static timing analysis, and power analysis
• Experience with Xilinx or Intel/Altera FPGA architectures and design tools
• Soft skills: Adaptive, creative, collaborative, comfortable working independently, enjoys solving difficult problems while communicating with all levels of an organization

Qualifications

Principal FPGA Design Engineer (Level 3): Minimum 5 years of FPGA/ASIC design experience (or MS + 3 years, or PhD).

Sr. Principal FPGA Design Engineer (Level 4): Minimum 8 years of FPGA/ASIC design experience (or MS + 6 years, or PhD + 3 years).

Preferred Qualifications

• Current or Active Top Secret with SCI/SAP security clearance
• Extensive experience implementing Digital Signal or Image Processing algorithms on FPGAs
• Experience with high-speed interfaces (e.g., AXI, PCIe, Xilinx Aurora, JESD, 10G Ethernet)
• Working knowledge of SDR platforms and architectures
• Experience developing FPGA algorithms for SoC-based architectures
• Experience developing FPGA/SW interfaces and controls
• Experience prototyping in MATLAB/Simulink
• Experience debugging down to the hardware level using Signal Generators, Logic Analyzers, Digital Oscilloscopes, and Embedded FPGAs
• Experience developing requirements for FPGA-based products
• Experience with EDA tools: Mentor Graphics ModelSim/QuestaSim, Synplify, Xilinx ISE/Vivado, Intel Quartus, Altera SOPC Builder, Altera Qsys, DSP Builder
• Experience with test benches using SystemVerilog and Universal Verification Methodology (UVM)
• Familiarity with revision control, documentation, planning, and review systems (e.g., GIT/SVN/ClearCase, DOORS, Jira/Rally/ClearQuest)

Pay

Principal FPGA Design Engineer (Level 3): $119,600.00 – $179,400.00

Sr. Principal FPGA Design Engineer (Level 4): $149,300.00 – $223,900.00

Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay. Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results. Employees in Vice President or Director positions may be eligible for Long Term Incentives.

Benefits

• Health insurance coverage
• Life and disability insurance
• Savings plan
• Company-paid holidays
• Paid time off (PTO) for vacation and/or personal business