Principal Product Development Engineer

About the role

The Principal Sr. Product Development Engineer will serve as the technical anchor for the Mixed-Signal Product Development team, driving the technical roadmap and processes from early silicon validation through qualification and high-volume manufacturing.

Responsibilities

• Drive the end-to-end technical product development strategy from early silicon validation through qualification and high-volume manufacturing.
• Define, develop, and implement advanced validation methodologies and innovative test strategies for deep-submicron analog and mixed-signal silicon builds.
• Work in close partnership with Analog/Digital Development, System Level Testing, groups dedicated to product validation, durability, and production.
• Influence strategies for design-for-test (DFT), design-for-manufacturability (DFM), and built-in self-test (BIST).
• Maintain consistent alignment from architectural codesign through to mass production.
• Coordinate and architect complex parametric, electrical, and mixed-signal characterization frameworks for high-speed interfaces, power management units, and clocking circuits.
• Lead deep-dive root-cause analysis and resolve highly complex technical anomalies related to silicon performance, Vmin/Fmax charting, yield excursions, and product reliability.
• Architect yield improvement initiatives, test time reduction strategies, and manufacturing efficiency improvements across wafer-sort and final packaged test flows.
• Provide structured, data-driven feedback to analyze silicon performance, design margins, process corners, and parametric sensitivities to improve future architectures.
• Establish scalable data analysis frameworks, automated data pipelines, and statistical methodologies for high-volume validation and production monitoring.

Requirements

• Master’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
• More than 12 years of background in semiconductor product development, validation, or manufacturing engineering.
• 12+ years of experience serving as a technical lead, principal engineer, or guiding cross-functional technical teams through product lifecycles.
• Extensive technical knowledge of advanced CMOS process technologies, analog/mixed-signal circuit behavior, and digital logic interaction.
• Proven experience in yield analysis, product characterization, and applying statistical data analysis tools (e.g., JMP, Spotfire) for engineering insights and data-driven yield improvements.
• High proficiency in automation and scripting (e.g., Python, MATLAB) for validation, data analysis, and test infrastructure.
• Proven capability to overcome significant cross-functional obstacles and lead problem-solving within tight delivery timelines.

Qualifications

• Extensive technical knowledge in foundry device physics and working closely with foundries to identify and address process anomalies and guide fab engineering teams to overcome major yield challenges.
• Deep expertise in defining ATE flows, structural and functional test pattern conversion, and handling high-power FinFET or gate-all-around (GAA) silicon.
• Background in multi-chip modules (MCM), 2.5D/3D packaging integration, or CoWoS technologies.
• Proven success leading silicon product ramps from low-yielding prototype phases to stable, high-volume manufacturing scale.

Skills

• Strong leadership and technical expertise in advanced CMOS nodes and high-speed mixed-signal systems.
• Experience in guiding complex product development lifecycles in high-volume semiconductor manufacturing.
• Proficiency in automation and scripting (e.g., Python, MATLAB) for validation, data analysis, and test infrastructure.
• Ability to overcome significant cross-functional obstacles and lead problem-solving within tight delivery timelines.
• Expertise in foundry device physics and working closely with foundries to identify and address process anomalies and guide fab engineering teams to overcome major yield challenges.
• Deep expertise in defining ATE flows, structural and functional test pattern conversion, and handling high-power FinFET or gate-all-around (GAA) silicon.
• Background in multi-chip modules (MCM), 2.5D/3D packaging integration, or CoWoS technologies.
• Proven success leading silicon product ramps from low-yielding prototype phases to stable, high-volume manufacturing scale.

Benefits

NVIDIA offers competitive compensation packages including base salary ranging from $240,000 to $379,500, along with equity and comprehensive benefits.

Pay

Base salary range: $240,000 - $379,500

Schedule

Full-time position