Principal Physical Design Engineer, Methodology

Key Responsibilities

• Define, develop, and maintain reusable physical design flows spanning synthesis, place-and-route, extraction, STA, and EMI.
• Evaluate and qualify new tool features, foundry enablement kits, and flow enhancements to continuously improve PPA and schedule predictability.
• Integrate and maintain DRC/LVS/extraction runsets and ensure consistency with foundry requirements.
• Build and enhance automation scripts and infrastructure to manage large-scale multi-corner/multi-mode STA and EMIR runs with efficient partitioning and resource usage.
• Develop QoR optimization frameworks and tracking methodologies to measure and improve design quality across programs.
• Partner with IT and compute infrastructure teams to optimize job scheduling, storage, and compute resource utilization.

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Masters Preferred.
• 8+ years of experience in physical design methodology, CAD, or flow development for complex SoCs at advanced nodes (7nm and below).
• Strong knowledge of synthesis, place-and-route, extraction, STA, and equivalence checking flows.
• Experience with both Cadence (Innovus, Tempus, Voltus, Pegasus) and Synopsys (Fusion Compiler, PrimeTime, StarRC, ICC2) toolchains.
• Expert-level scripting ability in Python, Tcl, and/or Perl for flow development and automation.
• Understanding of foundry design rules, technology files, and enablement kit integration.
• Ability to work independently with strong prioritization and a results-driven mindset.

Preferred Qualifications

• Knowledge of agentic AI solutions for EDA automation.
• Experience with CI/CD integration for physical design flows.
• Familiarity with compute farm management and job scheduling optimization.
• Knowledge of advanced packaging or multi-die integration flows.