Principal Packaging Engineer

Key Responsibilities

• Select and design optimal multi-die package types (MCM, 2.5D, 3D, fan-out, CoWoS, InFO, CPC, CPO) balancing electrical performance, thermal behavior, cost, and manufacturability.
• Define package specifications, bump map and ball map, interposer requirements, and mechanical constraints.
• Define substrate stack-ups, bump pitch, ball pitch, routing, via structures, and material choices for performance and manufacturability.
• Perform high-speed signal escaping, routing and power distribution network design.
• Manage subcontractors and work directly with TSMC and/or OSAT on bumping, substrate options, and advanced packaging flows.
• Partner with IC design, physical design, SI/PI, and board teams to ensure package requirements meet system-level needs.
• Evaluate emerging packaging technologies and drive adoption for next-generation products.
• Support package-level bring-up, failure analysis, debug and qualification.

Required Skills & Qualifications

• B.S./M.S. in Electrical Engineering or related field.
• Experience with multi-die package design and UCIe (AP/SP) integration.
• Understanding of substrate materials, stack-ups, and mechanical constraints.
• Familiarity with SI/PI concepts to collaborate effectively with electrical teams.
• Experience managing packaging subcontractors.
• Experience interfacing with TSMC/OSAT for bumping and packaging options.
• Knowledge of package modeling tools (HFSS, Sigrity, or similar) is a plus.

Compensation

Target base salary for this role is $180,000–$240,000 per year + meaningful equity + benefits + 401k. Our salary ranges are determined by role, level, experience, and location.