Principal / Lead Engineer

Role: Principal / Lead Engineer Location: San Jose, CA Let's create our future together at The AES Group! About The AES Group The AES Group is a premier technology and engineering consulting company that has been bringing businesses and talent together for over 20 years to deliver innovative solutions that make a positive impact. We help organizations modernize their technology through cloud, data, AI, engineering, cybersecurity, and emerging technologies. Job Summary We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet- based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities, contribute to Transaction Layer development, and work closely with Architecture, RTL, Verification, DFT, Physical Design, STA, and Silicon Validation teams. The ideal candidate should possess deep expertise in PCIe protocol, high-speed interfaces, subsystem integration, timing closure methodologies, and full ASIC development flow from architecture through silicon bring-up. Key Responsibilities Lead development and integration of PCIe Gen5/Gen6 Controller, PHY, and SerDessubsystems.Define subsystem architecture, interface specifications, microarchitecture, and designdocumentation.Participate in Transaction Layer development and enhancements.Support PCIe/CXL interoperability and advanced features.Drive integration of high-speed PHY and SerDes IPs. Work On Link trainingEqualizationPLL integrationReference clock architecturePIPE interfacesLane repair and lane aggregation Collaborate with analog and PHY teams during integration and debug. Work Closely With DV Teams To Define comprehensive verification plans.Review UVM-based test environments.Develop assertions and coverage metrics.Support protocol compliance testing.Debug simulation, emulation, FPGA, and post-silicon issues. Support DFT Implementation Including Scan insertionMBISTLBISTJTAG/Boundary ScanAt-speed testing Define test requirements for PCIe controller and PHY subsystems. Collaborate with DFT and silicon validation teams to achieve coverage target Develop And Maintain Subsystem-level SDC Constraints For SynthesisStatic Timing AnalysisPlace & RouteTiming signoff Work with PD and STA teams to achieve timing closure. Silicon Bring-Up & Debug Support PCIe link training debugCompliance testingSilicon characterizationPerformance tuning Analyze protocol traces and lab debug logs. Education B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or related discipline. With 10+ years of experience Masters degree preferred for Principal Engineer role.