Principal / Lead Engineer

About the role

The AES Group is a premier technology and engineering consulting company with over 20 years of experience delivering innovative solutions. We specialize in modernizing technology through cloud, data, AI, engineering, cybersecurity, and emerging technologies.

Key Responsibilities

• Lead development and integration of PCIe Gen5/Gen6 Controller, PHY, and SerDes subsystems.
• Define subsystem architecture, interface specifications, microarchitecture, and design documentation.
• Participate in Transaction Layer development and enhancements.
• Support PCIe/CXL interoperability and advanced features.
• Drive integration of high-speed PHY and SerDes IPs.
• Work on Link training, equalization, PLL integration, reference clock architecture, PIPE interfaces, lane repair, and lane aggregation.
• Collaborate with analog and PHY teams during integration and debug.
• Work closely with DV teams to define comprehensive verification plans, review UVM-based test environments, develop assertions and coverage metrics, and support protocol compliance testing.
• Debug simulation, emulation, FPGA, and post-silicon issues.
• Support DFT implementation including scan insertion, MBIST, LBIST, JTAG/Boundary Scan, and at-speed testing.
• Develop and maintain subsystem-level SDC constraints for synthesis, Static Timing Analysis (STA), Place & Route, and timing signoff.
• Collaborate with DFT and silicon validation teams to achieve coverage targets.
• Work with PD and STA teams to achieve timing closure.
• Support silicon bring-up and debug, including PCIe link training debug, compliance testing, silicon characterization, performance tuning, and analysis of protocol traces and lab debug logs.