Principal High-Speed I/O Architect (PCIe, CXL, UA Link)

About the role

At Arm, the High-Speed I/O Architect defines and designs innovative on-chip interconnect architectures—coherent and non-coherent—for scalable SoC platforms. You will work across markets including mobile, automotive, datacenter, networking, and IoT, contributing to production-quality silicon with top-tier performance and efficiency. Collaborating with multi-functional teams, you'll shape the interconnect infrastructure that powers next-generation SoCs.

Responsibilities

• Architect high-speed interconnect subsystems—including PCIe, CXL, and UA Link—and define coherent and non-coherent communication architectures across a range of silicon products.
• Define IP and subsystem roadmaps for high-speed I/O and interconnect technologies in close partnership with SoC architecture and core technology teams.
• Lead early architecture engagements with customers, shaping system requirements and delivering clear, implementation-ready specifications.
• Collaborate with performance, power, and physical design teams to optimize PCIe/CXL/UA Link subsystem behavior, bandwidth, latency, and overall system efficiency.
• Develop SoC architecture integrating Arm IP and high-speed I/O subsystems to meet compute, memory, and interconnect performance targets.
• Partner with software, firmware, and platform teams to optimize end-to-end solutions spanning hardware, drivers, and system software.
• Support detailed use-case exploration, workload analysis, and performance modeling to guide architectural decisions.

Required skills and experience

• 8+ years of experience with coherency protocols, hierarchical cache design, and system-level coherency architectures.
• Deep expertise in PCIe, CXL, and UA Link protocols, including link-level behavior, transaction flows, ordering models, memory expansion/pooling, die-to-die or chiplet connectivity, and host/device integration.
• Consistent track record collaborating with performance, power, and physical design teams on the PCIe, CXL, and UA Link stack.
• Strong knowledge in areas such as heterogeneous compute, PCIe/CXL/UA Link subsystem design, security, caching, memory systems.
• Demonstrated communication and leadership skills with the ability to influence executive stakeholders and multi-functional teams.
• Bachelor's or Master's degree (or equivalent) in Electrical or Computer Engineering with 10+ years of experience in semiconductor architecture, design, or related roles.

Nice to have

• Ability to thrive in dynamic environments with shifting priorities.
• Constructive, strategic approach to challenge and improve status quo.
• Track record of delivering complex projects on time and to spec.

Benefits

• Salary range: $249,900–$338,100 per year
• Competitive and equitable total reward package (additional components shared during recruitment)

Schedule

Hybrid working model designed to support high performance and personal wellbeing, with team-specific patterns determined collaboratively.