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Principal FPGA/ASIC Verification Engineer (Onsite)- Active Secret

Collins Aerospace · Fort Wayne, IN · 2 wk ago
On-siteQuality AssuranceFull-time

About the role

At RTX, the world's largest aerospace and defense company, 185,000 great minds are united by purpose and inspired to make a difference solving the world’s most complex problems. With our three market leading businesses, world-class operations and investments in research and development, we offer capabilities and opportunity no one else can. Together, we push the boundaries of known science and find new ways to connect and protect our world. Collins Aerospace is a leader in technologically advanced, intelligent solutions that help redefine the aerospace and defense industry. With a comprehensive portfolio and deep technical expertise, we help customers meet the demands of the global market. Join us and help shape the future of aerospace and defense.

Responsibilities

  • Verification environment architecture and design using SystemVerilog with OVM/UVM
  • Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow
  • Contribute to engineering estimates for new program pursuits.
  • Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Requirements

  • Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience
  • Active and transferable U.S. government issued security clearance is required prior to start date
  • U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
  • At least 4+ years experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
  • Demonstrated ability to work independently and lead and/or mentor junior engineers within a team environment
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
  • 4+ years of experience

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