Principal Firmware/Middleware Engineer

Renesas is a top global semiconductor company developing solutions for a safer, healthier, greener, and smarter world. Our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure, and IoT markets. With a robust product portfolio including world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions, we are a key supplier to leading electronics manufacturers. Renesas employs roughly 21,000 people in more than 30 countries worldwide, embodying a culture based on transparency, agility, global collaboration, innovation, and entrepreneurship.

About the role

As the Principal Firmware Architect for UALink Switch Products, you will serve as the technical visionary responsible for defining, designing, and driving the end-to-end embedded software and firmware architecture for next-generation AI cluster scale-up switches. You will bridge the gap between cutting-edge silicon (ASICs) and upper-layer cluster orchestration software, defining how firmware manages complex scale-up topologies, ensures raw hardware performance, and maintains absolute reliability across thousands of connected AI accelerators.

Responsibilities

• Architectural Definition & Design
  • Fabric Firmware Architecture: Architect and specify the low-level firmware running on internal microcontrollers within the UALink Switch ASIC.
  • Hardware-Software Co-Design: Collaborate with ASIC design, logic design (RTL), and verification teams to define hardware-software interfaces, registers, scratchpads, and memory maps.
  • Protocol Implementation: Define the firmware stack to support UALink physical, link, and transport layers, managing credits, routing tables, and flow control.
• Initialization, Boot, & Fabric Management
  • Link Initialization & Training: Design deterministic, fast link-training state machines to bring up ultra-high-speed die-to-die and chassis-to-chassis UALink connections.
  • Topology Discovery & Routing: Architect efficient algorithms for runtime topology discovery, dynamic routing, and credit management to prevent fabric congestion.
  • Platform Orchestration: Lead the design of SDKs and APIs that expose switch functionality to baseboard management controllers (BMCs) using OpenBMC and Redfish APIs.
• Performance, RAS, & Security
  • Latency & Bandwidth Optimization: Fine-tune bare-metal execution paths to guarantee deterministic low latency for collective communication primitives (e.g., All-Reduce, All-to-All).
  • Advanced RAS (Reliability, Availability, Serviceability): Design robust error-handling, telemetry, and fault-isolation micro-architectures (e.g., link degradation fallback, FEC, and error containment).
  • Security & Root of Trust: Implement secure boot, cryptographic firmware authentication, and runtime attestation to ensure fabric integrity.

Requirements

• Education & Experience: Bachelor’s or Master’s/Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related discipline. 15+ years of hands-on experience in embedded systems, server platform architecture, or low-level silicon firmware development.
• Technical Skill Set:
  • Language Masteries: Expert-level proficiency in C for bare-metal and RTOS environments (e.g., ThreadX, FreeRTOS, Zephyr) and Python for hardware automation and modeling.
  • Protocol Expertise: Deep technical understanding of high-speed scale-up/scale-out interconnect protocols (UALink, NVLink, CXL, or PCIe Gen5/Gen6).
  • Network Switching Concepts: Comprehensive knowledge of credit-based flow control, packet routing, physical layer (PHY) equalization, and SerDes management.
  • Tooling: Strong familiarity with hardware debuggers (JTAG, Lauterbach/TRACE32) and lab equipment (Oscilloscopes, PCIe/Protocol Analyzers).

Benefits

Renesas offers a competitive benefits package alongside salary. More information will be provided during the hiring process.