Principal Engineer Verification & Validation

About the role

As a Principal Engineer Verification & Validation on our Research & Development team, you'll shape the future of technology by driving groundbreaking projects and bringing new ideas to life. This role merges creativity with technical expertise to deliver thoroughly verified, robust semiconductor IP and systems.

Responsibilities

• Participate in architecture definition and modeling
• Contribute to micro-architecture definition and reviews
• Review standard specs and incorporate changes into the verification plan to ensure compliance
• Define verification strategy (constraint random, Formal, Directed, etc.) for IP/Chip/System level verification
• Define and implement verification environment architecture and methodology development
• Drive block/chip/system level test plan development and execution
• Work with ASIC designers and architects to produce thoroughly verified, robust IP
• Oversee all verification for the IP/Chip/System and drive functional and code coverage closure
• Actively participate in post-silicon bring-up, validation, and compliance testing
• Collaborate cross-functionally with design, software, and hardware teams to ensure successful product delivery
• Mentor other engineers and provide technical guidance

Requirements

• Minimum a Bachelor’s Degree (or foreign equivalent) in Electrical Engineering, Electronic Engineering, or a related field
• 6-8 years of experience in verification and validation
• Working knowledge of gate-level simulation and power-aware simulations
• Proficient in object-oriented programming and development of reusable testbenches
• Experience working with verification IPs
• Experience implementing constraint random verification methodology
• Strong problem-solving skills and ability to work effectively with internal and external teams/customers
• Experience with silicon debug, including logic and custom Analog Blocks
• Understanding of performance and latency verification
• Self-motivated with initiative to seek constant improvements in verification methodologies
• Proven track record of taking IPs from product definition to production
• Experience in complex IP verification
• Good understanding of IP design and verification methodologies and flows
• Solid understanding of standard IP verification techniques

Pay

The expected wage range for this role in San Jose, CA is $147,400 – $202,700 per year. All employees are also eligible to participate in an incentive plan.