Principal Engineer, Post-silicon Validation

About the role

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD, MediaTek and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures. In this role, you will lead the silicon validation of our optical chiplets. You will define and drive the validation strategy from initial silicon power-on through block and chip level signoff. This is a rare opportunity to apply deep expertise in high-speed SerDes, photonic systems, and post-silicon validation to shape the future of optical interconnect for next-generation AI infrastructure. Location: San Jose (on-site).

Responsibilities

• Lead Validation Strategy: Define and implement comprehensive validation methodologies for our electronic-photonic SoCs, covering initial bringup, functional validation, electrical characterization, and system-level testing. Develop detailed test plans, success criteria, and select appropriate test equipment and methodologies.
• Drive Silicon Bring-up: Lead first silicon power-on and bringup for new tape-outs, collaborating with firmware and design teams to establish operating conditions and validate core functionality from day one.
• Own Block and System Validation: Execute rigorous post-silicon validation of SerDes interfaces, optical control loops, and mixed-signal blocks using industry-standard lab equipment (BERT, DCA, oscilloscopes, OSA, VNA).
• Apply Standards and Best Practices: Draw on industry standards (IEEE, OIF, JEDEC, Ethernet/Optical MSA specs) and semiconductor validation best practices to establish rigorous validation targets, coverage objectives, and signoff criteria.
• Root Cause and Debug: Investigate and drive to closure all silicon failure modes, from signal integrity issues to mixed-signal anomalies, using systematic debug methodologies and close collaboration with design and firmware teams.
• Mentor and Lead: Provide technical leadership and mentorship to senior and junior validation engineers; guide the team's technical execution.
• Deliver High Quality Documentation: Create and maintain comprehensive validation reports, signoff packages, and product performance documentation.

Requirements

Bachelor's degree in Electrical Engineering or related field with 10+ years of relevant industry experience, or Master's degree with 7+ years of experience.

Demonstrated leadership in post-silicon validation for complex SoCs or multi-chip packages, including first silicon bringup and full signoff.

Skills

• Hands-on expertise with high-speed SerDes validation and characterization (NRZ and PAM-4) using equipment such as BERTs, oscilloscopes/DCAs,