Principal Engineer, NPU Architect

Job Description

We are looking for a Principal NPU Hardware Architect with 10 to 15 years of experience to drive the architectural definition and hardware implementation of high-performance Neural Processing Units (NPUs) targeted for microcontrollers and microprocessors addressing Automotive high performance compute.

Responsibilities

• NPU Architecture & Dataflow: Define and own the end-to-end NPU micro-architecture, including high-throughput tensor/matrix engines, vector units, and specialized activation functional units.
• Hardware-Software Co-Design: Partner closely with compiler and software teams to define instruction sets (ISA), memory management schemes, and hardware-aware graph optimizations.
• Virtualization & Multi-Tenancy: Architect hardware-assisted virtualization features to enable secure resource sharing and multi-tenant execution in cloud or edge environments.
• Interconnect & Fabric: Design and integrate high-bandwidth Bus fabrics (e.g., NoC, CHI) and DMA controllers optimized for the massive data movement inherent in AI workloads.
• Infrastructure & Power: Lead the definition of SoC infrastructure elements, including complex clock/reset domains and advanced power management strategies to maximize performance-per-watt.
• Performance Modeling: Develop bit-accurate and cycle-accurate C++/SystemC models to validate architectural choices and enable early software development.
• Full Design Flow: Oversee the transition from architectural spec to RTL, providing technical leadership through verification, physical design, and post-silicon bring-up.

Qualifications

• Education: Bachelor’s or Master’s in Electrical Engineering or Computer Engineering (PhD desirable)
• Experience: 12+ years in AI accelerator, NPU, or GPU hardware architecture and RTL design.
• Domain Expertise: Deep knowledge of deep learning primitives (CNNs, Transformers, RNNs) and how they map to spatial compute hardware.
• Software Awareness: Strong understanding of compiler backends (e.g., LLVM, MLIR), IR transformations, and how hardware features like scratchpad memories or tiling impact compiler efficiency.
• System Integration: Proven track record with modern SoC protocols (AXI/ACE/CHI) and integrating NPU cores into larger system-on-chip environments.
• Modeling Skills: Expert-level proficiency in SystemC/TLM or C++ for architectural performance modeling and hardware-software co-verification.
• Leadership: Ability to act as a technical authority, mentoring junior designers and influencing cross-functional roadmaps.

Additional Information

Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.

Renesas is an equal opportunity and affirmative action employer, committed to celebrating diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by federal, state or local law. For more information, please read our Diversity & Inclusion Statement.

Renesas Electronics is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in compliance with applicable laws. If you need a reasonable accommodation due to a disability during the application or interview process, please let us know at [email protected].

We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning.