Principal Engineer - HIG HBM - ARCHITECTURE

About the role

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The High-Performance Integrated Group (HIG) develops next-generation High Bandwidth Memory (HBM) solutions for AI, machine learning, and high-performance computing applications. We are seeking an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. This role focuses on PHY IO architecture, timing methodology, analog calibration schemes, and silicon learning frameworks that enable industry-leading bandwidth, power efficiency, and robustness. The successful candidate will collaborate across Design, Product Engineering, Modeling, Verification, Packaging, and System Architecture teams to define architectural requirements, drive technology innovation, and ensure successful translation from concept to silicon. As a technical leader, you will influence future HBM roadmap decisions, develop engineering methodologies, and mentor design teams on architectural principles, calibration strategies, and best practices for high-speed IO design.

Responsibilities

• Define and drive next-generation HBM PHY and IO architecture, balancing performance, power, area, reliability, and manufacturability requirements.
• Architect high-performance transmit and receive paths, including clocking, signaling, equalization, timing alignment, and interface optimization.
• Define and optimize analog calibration architectures, including impedance calibration, reference voltage calibration, timing calibration, and adaptive tuning methodologies.
• Develop and maintain IO timing budgets, design targets, and margin methodologies across process, voltage, temperature, and package variations.

Qualifications

Required:

• MS or PhD in Electrical Engineering or a related field.
• 7+ years of experience in semiconductor design, architecture, or technology development.
• Demonstrated expertise in analog and mixed-signal IO design and architecture.
• Deep knowledge of high-speed transmitter, receiver, clocking, and timing architectures.
• Strong technical communication and documentation skills.

Preferred:

• Experience with HBM, DDR, UCIe, PCIe, or other high-speed memory and interconnect technologies.
• Experience developing and evaluating analog calibration schemes, including impedance calibration, reference voltage calibration, timing calibration, adaptive and background calibration techniques.
• Experience with advanced packaging technologies, including 2.5D, 3D integration, and TSV-based systems.
• Background in clock generation, clock distribution, PLLs, phase alignment, or timing recovery circuits.
• Experience with silicon bring-up, product engineering, or post-silicon debug.
• Demonstrated use of AI-enabled analytics or automation techniques to improve design quality, silicon analysis, or engineering productivity.
• Experience developing design methodologies, architecture standards, and engineering training material.