Principal Engineer Digital Design

About the role

As a Lead Principal Engineer Digital Design in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life.

Responsibilities

• Implement DSP algorithms (e.g., Filtering, Error Correction coding, Echo Cancellation, Receiver Equalization and so on) in Verilog/System Verilog, ensuring adherence to design specifications
• Collaborate with algorithm and systems teams to define hardware architecture
• Translate fixed-point MATLAB/C/C++ models into fixed-point, synthesizable HDL code
• Conduct performance analysis, optimizing for latency, throughput, power, and area (PPA)
• Create design documentation and work with the DV team to verify functionality
• Support ASIC synthesis, timing closure, and silicon debugging

Qualifications and Skills

• Bachelor’s or Master’s degree in EE/Computer Engineering
• 12+ years of experience in RTL design (Verilog/System Verilog)
• Strong knowledge of fixed-point math for signed binary numbers (such as sign-extension, addition, multiplication, rounding and saturation), and digital signal processing fundamentals
• Proven experience in implementing DSP algorithms on FPGA or ASIC
• A certain degree of understanding in MATLAB/Simulink/C/C++
• Experience with EDA tools (e.g., Synopsys Design Compiler, Cadence)
• Excellent problem-solving skills and teamwork

Pay

• Irvine, CA: Minimum of $175,300 salary per year / Maximum of $241,000 salary per year
• Dallas, TX: Minimum of $164,400 salary per year / Maximum of $226,100 salary per year

Schedule

• Full-time

Benefits

• All employees will be eligible to participate in an incentive plan.