Principal Engineer - Analog and Mixed-Signal Physical Design

About the role

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and is responsible for powering Microsoft’s Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft’s online businesses, including Azure, Microsoft 365, Teams, OneDrive, Xbox, and other global services.

We are looking for a Principal Engineer – Analog and Mixed-Signal Physical Design to serve as a hands-on technical contributor who can drive physical implementation, timing closure, physical design verification, and custom IP integration for analog and mixed-signal designs. This is a hands-on Principal role, not a planning-only or coordination-only position.

Responsibilities

• Drive hands-on physical design implementation for analog and mixed-signal IP blocks, including floorplanning, placement, routing, optimization, ECO implementation, and closure debug.
• Execute and guide Fusion Compiler-based APR flows, with direct ownership of implementation quality, timing convergence, physical design verification readiness, and signoff closure.
• Serve as the technical bridge between analog design, custom layout, physical design, timing, physical verification, CAD/methodology, and silicon integration teams.
• Perform timing analysis and closure activities across analog and mixed-signal-adjacent IP, including constraint review, timing debug, implementation tradeoffs, and signoff readiness.
• Partner with custom layout engineers to ensure layout feasibility, integration quality, physical verification closure, and timing/implementation convergence without positioning this role as a pure custom layout owner.
• Lead internal and external/V-team execution through hands-on technical direction, deliverable review, quality expectations, and schedule alignment.
• Debug and resolve complex implementation issues related to physical design, timing closure, extraction, physical verification, layout integration, reliability, and release readiness.
• Coordinate implementation activities across architecture, circuit design, layout, CAD/methodology, verification, product engineering, and silicon integration stakeholders.
• Contribute to design reviews, implementation quality improvements, signoff planning, and broader execution strategy for analog, mixed-signal, and custom IP physical design deliverables.
• Mentor engineers and provide Principal-level technical leadership while remaining directly engaged as a doer in critical implementation and closure work.

Qualifications

Required Qualifications

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information controlled for export under regulations such as the U.S. International Traffic in Arms Regulations, Export Administration Regulations, or the EU Dual Use Regulation. Proof of citizenship, U.S. residency, or other protected status may be required as a condition of employment.

Preferred Qualifications

• Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field AND 10+ years of technical engineering experience in silicon development, physical design, timing closure, or related disciplines.
• Experience with analog and mixed-signal IP physical implementation, custom IP integration, or mixed-signal-adjacent implementation flows.
• Knowledge of PrimeTime timing analysis, constraint debug, timing ECO strategy, and timing closure methodologies.
• Working understanding of custom analog layout, Virtuoso-based layout methodologies, physical verification, extraction, and layout integration considerations.
• Familiarity with advanced-node implementation challenges and cross-functional integration across architecture, circuit design, layout, CAD/methodology, product engineering, and silicon integration teams.
• Strong debugging, analytical, problem-solving, communication, and cross-functional collaboration skills.
• Proven Principal-level technical leadership across large-scale, cross-functional engineering efforts while remaining hands-on in execution.
• Experience with Fusion Compiler-based APR and physical implementation flows, including floorplanning, placement, clock tree synthesis, routing, optimization, ECO implementation, and closure debug.
• Experience with physical design verification, implementation signoff, and silicon quality methodologies.
• Experience performing hands-on physical implementation and timing closure for complex silicon IP from concept through tapeout or equivalent silicon development milestones.
• Experience leading or coordinating distributed engineering teams, including vendor or external/V-team resources, while remaining directly involved in technical execution.

Pay

The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. For specific work locations within the San Francisco Bay area and New York City metropolitan area, the base pay range is USD $188,000 - $304,200 per year. Certain roles may be eligible for benefits and other compensation.