Principal Electrical Engineer – DSP ASIC/FPGA (Onsite)

About the role

RTX Corporation is seeking a highly skilled and innovative Principal DSP FPGA/ASIC Engineer to join our Applied Research and Technology team in Cedar Rapids, Iowa.

Responsibilities

• Develop and implement signal processing algorithms for FPGA or ASIC based systems.
• Utilize Simulink for modeling and simulation of signal processing systems and workflows.
• Collaborate with cross-functional teams to design, test, and validate DSP algorithms for real-world applications.
• Optimize FPGA implementations to meet performance, power, and size constraints.
• Conduct system-level analysis and testing to ensure adherence to project requirements.
• Provide technical guidance and mentorship to junior engineers and contribute to the overall technical roadmap of the team.
• Work closely with hardware, software, and systems engineers to integrate signal processing solutions into larger systems.

Requirements

• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 8 years prior relevant experience or an Advanced Degree in a related field and minimum 5 years of experience.
• The ability to obtain and maintain a U.S. government issued secret security clearance is required.
• Strong expertise in Simulink and/or MATLAB for modeling and simulation of DSP systems.
• Proficient in VHDL/Verilog for FPGA/ASIC design and implementation.
• Demonstrated experience with algorithm development for signal processing applications such as filtering, modulation, demodulation, and spectral analysis.
• Familiarity with FPGA platforms such as AMD (Xilinx), Intel (Altera), or others, and associated toolchains (e.g., Vivado, Quartus).
• Strong debugging and troubleshooting skills for FPGA/ASIC and DSP systems.

Qualifications

• Experience with high-speed digital interfaces and protocols (e.g., DDR, PCIe, Ethernet) is preferred.
• Excellent communication and teamwork skills with the ability to work in a collaborative environment.
• Familiarity with HDL Coder and generation of HDL from model-based designs is preferred.
• Background in aerospace, defense, or mission-critical systems is preferred.
• Understanding of hardware-software co-design principles is preferred.