Principal DFT Architect

About the role

The DFT Architect at Altera is a senior technical authority responsible for defining, driving, and governing next-generation DFT architecture across Altera’s most advanced FPGA, SoC, and multi-die silicon platforms. This role sits at the forefront of innovation in high-performance compute, AI acceleration, advanced packaging, and heterogeneous integration.

Responsibilities

• DFT Strategy Ownership: Define and drive the long-term DFT architecture for FPGA, SoC, processor, DSP, SERDES, IO, and multi-die/chiplet-based products.
• Methodology Leadership: Lead development of scalable DFT methodologies and flows across RTL, gate-level, hierarchical, and multi-die integration environments.
• Advanced DFT Architecture: Architect state-of-the-art scan, compression, ATPG, MBIST, LBIST, boundary scan, and in-system test solutions to meet aggressive coverage, quality, and cost goals.
• Multi-Die & Advanced Packaging DFT: Drive DFT planning and integration for 2.5D/3D ICs, chiplets, and heterogeneous multi-die systems.
• Cross-Functional Integration: Collaborate with architecture, RTL, PD, STA, validation, and product engineering teams to ensure seamless DFT integration throughout the design lifecycle.
• DFT Governance: Establish and enforce DFT guidelines, test specifications, timing constraints, and signoff criteria across large engineering programs.
• Silicon Debug Leadership: Lead root-cause analysis for pre-silicon and post-silicon test failures, yield issues, and manufacturing escapes.
• Manufacturing Test Optimization: Optimize production test strategies for coverage, test time, yield improvement, power-aware test, and overall efficiency.
• Technology Innovation: Drive adoption of next-generation DFT technologies, automation, and best practices to improve productivity and scalability.
• Technical Mentorship: Mentor DFT engineers and provide technical leadership across multiple programs.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 15+ years of industry experience.
• 10+ years architecting and implementing DFT solutions for complex SoC, FPGA, ASIC, or multi-die designs.
• 10+ years experience in scan architecture, ATPG, compression, MBIST, LBIST, boundary scan, and hierarchical DFT.
• 10+ years experience with RTL-to-GDS DFT integration including scan insertion, STA constraints, low-power DFT, and gate-level verification.
• 10+ years experience with industry-standard EDA tools for synthesis, scan insertion, ATPG, simulation/debug, formal verification, and STA.
• 10+ years experience supporting silicon bring-up, manufacturing test flows, yield analysis, and failure debug.
• 10+ years experience developing DFT automation using scripting languages (Perl, Python, TCL).
• 10+ years experience providing technical leadership and driving cross-functional alignment.