Principal Design Verification Engineer – CPU Core Hardware Prefetch

Responsibilities

• Lead verification planning and execution for CPU hardware prefetch functionality in a high-performance out-of-order core, with ownership spanning unit-level and core-level verification strategy, debug, coverage closure, and signoff readiness.
• Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for advanced hardware prefetch microarchitecture and its corner cases.
• Drive verification of hardware prefetch behaviors including stream allocation and replacement, training from demand requests, prefetch generation, request replay and kill behavior, issue-queue interactions, and feedback-driven control of prefetch aggressiveness.
• Verify correctness of runtime configurability through hardware prefetch CSRs, including enablement, windowing, initial distance, maximum allowed distance, linear-to-exponential growth thresholds, queue-allocation controls, and thresholds tied to L1/L2 cache and MSHR behavior.
• Drive verification of interactions between the hardware prefetch engine and the memory hierarchy, including DCache pipeline behavior, cacheable-read-only training conditions, MSHR fullness backpressure, L1/L2 prefetch targeting, and arbitration with other core-generated traffic.
• Develop verification strategies for difficult corner cases such as stream misconfirmation and untraining, queue unavailability, threshold-triggered throttling, page-boundary behavior, multi-stream behavior, and correctness under diverse operating modes and software-programmed configurations.
• Use architectural counters, self-checking tests, and microarchitectural observability to validate that prefetch behavior is both functionally correct and robust across realistic performance-sensitive traffic patterns.
• Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, improve debugability, and influence the design from a verification perspective.
• Apply the right verification method for the problem, including simulation, formal techniques, emulation, and performance-oriented validation where appropriate for high-risk or hard-to-observe hardware prefetch behaviors.
• Drive efficient failure analysis and root-cause debug across specification, RTL, test content, assertions, and verification infrastructure.
• Mentor engineers across the organization and shape reusable verification approaches, infrastructure, and methodology for future CPU core generations.

Qualifications

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 12+ years of relevant experience in CPU/core or SoC functional verification, with substantial experience appropriate for a Principal / T6 role.
• Direct experience with out-of-order CPU core verification and strong understanding of CPU microarchitecture.
• Deep expertise in hardware prefetch verification or closely related CPU memory-subsystem verification, with the ability to translate architectural intent into an effective verification strategy and execution plan.
• Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong debug skills and strong software or scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.
• Strong understanding of CPU memory behavior, including ordering-sensitive interactions, cache hierarchy effects, and how hardware prefetch interacts with demand traffic and system performance.