Principal Design Verification Engineer

Job Summary

We are seeking an experienced Principal Design Verification Engineer to lead verification activities for complex SoC/ASIC designs. The ideal candidate will have strong expertise in SystemVerilog, UVM, and functional verification, along with a proven track record of successful SoC tape-outs.

Responsibilities

• Lead Design Verification efforts for complex SoC projects
• Develop and maintain verification environments using SystemVerilog and UVM
• Create verification test plans, develop tests, and drive coverage closure
• Debug verification failures and work closely with design teams
• Develop automation tools using Python or Perl
• Support boot code verification and multi-core SoC validation
• Mentor and lead verification engineers

Requirements

• 10+ years of Design Verification experience (or MS/PhD with 5+ years)
• Strong experience with SystemVerilog and UVM
• Expertise in constrained-random and coverage-driven verification
• Python or Perl scripting experience
• Strong Linux, C++, and Object-Oriented Programming skills
• ARM Assembly experience preferred

Qualifications

• BS/MS/PhD in Computer Engineering, Electrical Engineering, Computer Science, or related field

Skills

• SystemVerilog
• UVM
• Functional verification
• Constrained-random and coverage-driven verification
• Python or Perl scripting
• Linux, C++, and Object-Oriented Programming
• ARM Assembly

Benefits

• Relocation Assistance Available
• Visa Sponsorship Available

Pay

$158,600 - $317,800 Bonus + RSUs

Schedule

Onsite in Santa Clara, CA