Pre‑Silicon Power Modeling Leader — x86 SoCs

About the Role

AMD’s embedded and client x86 programs demand first-time-right silicon. You will lead SoC-level pre-silicon power modeling—owning the methodology, models, and cross-functional influence that translate into accurate Perf/Watt projections, robust DVFS/AVFS plans, and silicon correlation that de-risks program power budgets.

Responsibilities

• Own the SoC power model end-to-end using AMD’s converged methodology, delivering accurate workload-based power estimates for CPU/GPU/NPU, fabric/interconnect, memory, and I/O.
• Define use-case power envelopes across automotive, networking, storage, industrial, and robotics segments; partner with product/marketing to derive representative workloads and KPIs.
• Drive DVFS/AVFS strategy (P-states, C-states, voltage/frequency points), telemetry requirements, and FW hand-offs based on model outputs; provide early tables and guardrails to FW/BIOS.
• Establish IP/subsystem power budgets; run sensitivity studies to guide architectural decisions (e.g., cache sizes, fabric frequencies, NPU/GPU configurations).
• Build repeatable model-to-silicon correlation plans (CaC/static/dynamic splits, EDC/TDC interactions, droop mitigation) and maintain a power scorecard for program reviews.
• Lead tool flows & automation (e.g., PowerArtist, PrimeTime PX; Python-based pipelines) to ingest activity (FSDB/VCD), generate reports, and publish dashboards for stakeholders.
• Collaborate across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes from concept through bring-up.

Requirements

• Demonstrated experience building top-level SoC power models with high correlation to silicon, including IP-level VBM integration and workload-based projections.
• Hands-on with EDA/tooling: PowerArtist, PrimeTime PX (or equivalents), activity annotation (FSDB/VCD), UPF/CPF power intent, Python for automation.
• Deep knowledge of x86 micro-architecture (CPU pipelines, caches), GPU/NPU basics, memory subsystems, interconnect/fabric behavior, and power delivery/PDN interactions.
• Proven ability to define DVFS/AVFS strategies and drive FW telemetry requirements; familiarity with EDC/TDC/CaC semantics and their impact on power.
• B.S./M.S. in EE/CE/CS (or related) with strong industry experience in SoC pre-silicon power modeling/estimation and cross-domain collaboration.

Preferred Experience

• Segment experience modeling power for automotive (AEC-Q100/ASIL) use-cases, networking throughput workloads, storage I/O patterns, industrial/robotics duty cycles.
• System performance modeling familiarity (GEM5/Simics/SystemC) to align Perf/Watt predictions and bottleneck analysis with architecture teams.
• Experience creating PnP dashboards/regressions (Python/Jenkins/Grafana/InfluxDB) for continuous tracking.

Deliverables

• A validated SoC power model & scorecard that anchors program power budgets and executive reviews.
• Workload-specific DVFS/AVFS tables and telemetry specs for FW/BIOS enablement.
• Correlation reports (estimated vs. measured) and recommendations that accelerate first-time-right silicon.

Location

Austin, TX (Hybrid)

This role is not eligible for visa sponsorship.

Benefits

Benefits offered are described: AMD benefits at a glance.