Power Management Design Engineer

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms enable leading technology companies to innovate, optimize, and deliver advanced solutions across markets including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

Our constant innovation and success are driven by our talented teams, who collaborate to create groundbreaking solutions that impact people's lives—making the world a better place, one processor at a time.

About the Role

SiFive is looking for hardware engineers passionate about designing industry-leading CPU and interconnect IP to drive the adoption of RISC-V as the architecture of choice for SOC designs across a broad variety of applications. We’re creating massively customizable IP and improving time-to-market by designing hardware as highly-configurable generators, leveraging technology and ideas from the software industry to execute hardware design with the agility of software development.

As a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer at SiFive, you will join a team designing industry-leading CPU cores and subsystems based on the open RISC-V and TileLink architectures. You will create power management, reset, and clocking solutions that serve as the central nervous system for cutting-edge RISC-V CPU and SoC IP designs. You will work in a fast-paced environment to bring new hardware IP to market quickly, with high quality and exceptional performance.

Responsibilities

• Work with the architecture team to understand and define power management requirements.
• Architect, design, and implement core clocking, reset, and power management solutions.
• Develop and specify microarchitecture.
• Ensure knowledge is shared via clear documentation and participation in a collaborative design culture.
• Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
• Work with the physical implementation team to implement and optimize physical design to meet frequency, area, and power goals.
• Collaborate with the software team to enable and optimize power management features.

Requirements

• 3+ years of recent industry experience in CPU and SoC clocking, reset, and power-management logic designs.
• Experience in high-performance, energy-efficient CPU and SoC designs.
• Expertise in CPU and SoC clocking, reset design, and power management, including:
  • Reset control and design strategies
  • Clock distribution, dynamic clocking, clock gating, and clock boundary crossing strategies
  • Power state definition and management and Power Management Unit (PMU) design
  • Dynamic and static power reduction techniques, including retention and power-up/down sequencing
  • Dynamic voltage and frequency scaling (DVFS) and Di/dt mitigation strategies
• Understanding of DFT, MBIST, Debug, and Error handling in CPU designs.
• Proficiency with hardware (RTL) design in Verilog, SystemVerilog, or VHDL.
• Good understanding of RTL quality checks like Lint, CDC, RDC (hands-on experience with Spyglass is a plus).
• Attention to detail and a focus on high-quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object-oriented and/or functional programming language.
• Background of successful CPU or SoC development from architecture through tapeout.
• BS/MS degree in EE, CE, CS, or a related technical discipline, or equivalent experience.

Nice to Have

• Experience with AMBA Interconnect Protocols, such as AXI, AHB, and APB.
• Experience with AMBA Low Power Protocol Interface, including P-channel and Q-channel protocols.
• Experience with Scala/Chisel, Bluespec, or other languages/DSLs for expressing configurable hardware via software.
• Knowledge of RISC-V architecture.
• Experience with Git/Github, Jira, Confluence.

Benefits

• Flexible paid time off.
• Health, vision, and dental benefits.
• 401(k) plan.
• Employee stock option program.

Pay

SiFive has a market-based pay structure which varies by location. The base pay range is a guideline reflecting the cost of labor in the U.S. geographic market based on the role’s location. Pay within this range varies depending on job-related knowledge, skills, and relevant work experience. The starting salary will be determined by qualifications such as skill level, competencies, and work location.

Base Pay Range: $139,752.00–$170,808.00

In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The role is also eligible for a comprehensive benefits package including healthcare and retirement plans, paid time off, and more.