Post silicon validation engineer

About the role

We are seeking a Post-Silicon Validation Engineer to drive the bring-up, characterization, and debugging of our next-generation Ethernet and PCIe Retimer chips. This role heavily focuses on advanced Ethernet physical layer (PHY) validation, ensuring our silicon meets rigorous IEEE networking standards and high-speed interoperability requirements.

Responsibilities

• Ethernet & PCIe Validation: Hands-on bring-up of multi-rate Retimer ICs.
• Compliance & Interoperability: Validate Ethernet (100G/400G/800G) and PCIe (Gen 5/6) for IEEE and PCI-SIG compliance.
• Automation: Build Python-based automated test frameworks for Ethernet throughput, BER, and control path testing which includes ARM based micros and GPIO/MDIO/I2C protocols.
• Network Debugging: Root-cause complex silicon, link training, and firmware bugs using protocol analyzers and traffic generators.

Requirements

• Ethernet Domain Knowledge: Expertise in Ethernet PHY architecture, PAM4/NRZ signaling, FEC (Forward Error Correction), Auto-Negotiation, and Link Training.
• Lab Equipment: Proficiency with high-bandwidth Oscilloscopes, BERTs, Ethernet Traffic Generators/Network Analyzers (e.g., Ixia, Spirent), and PCIe Analyzers.
• Programming/Scripting: Strong Python for lab automation and data analysis, plus C/C++ for low-level register manipulation.

Qualifications

Bachelors in Engineering and 8+ years of related experience or Masters degree in Engineering and 6+ years of related experience

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company paid holidays, paid sick leave and vacation time

Pay

The annual base salary range for this position is $108,000 - 172,800. This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.