Physical Design Engineer (Place & Route)

About the role

Astera Labs (NASDAQ: ALAB) seeks a Physical Design Engineer (Place & Route) to support the design of our portfolio of connectivity ASICs. This role is critical in planning, coordinating, and executing the design process, ensuring that our products meet the needs of leading cloud service providers, server, and network OEMs.

Responsibilities

• Drive complex SoC/silicon product designs from RTL to GDSII, with responsibility for multiple blocks.
• Collaborate with designers, verification engineers, and engineering operations to ensure successful block-level ownership and timely delivery.
• Develop and maintain timing constraints, perform timing closure at the block or full-chip level.
• Work with IP vendors for both RTL and hard-macro blocks, integrating high-speed SERDES or Ethernet PHY design as needed.
• Implement design for test (DFT) practices, including familiarity with ECO methodologies and tools.
• Optimize clock tree synthesis and ensure compliance with PCIe, CXL, or Ethernet connectivity protocols.

Requirements

• Bachelor's or Master's degree in Electrical Engineering or Computer Engineering.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications.
• Strong hands-on experience with synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence), and other backend tools and methodologies for technologies 7nm or less.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity with SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, and physical sign-off.
• Good scripting skills in Tcl, Python, or Perl.

Qualifications

• Strong academic and technical background in electrical engineering.
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
• Entrepreneurial, open-minded behavior and can-do attitude, thinking and acting fast with the customer in mind.

Skills

• Hands-on and thorough knowledge of synthesis, place and route, timing, extraction, EM-IR, formal verification (equivalence) and other backend tools and methodologies for technologies 7nm or less.
• Block level ownership from architecture to GDSII, driving multiple complex designs to production.
• Experience with Cadence and/or Synopsys physical design tools/flows.
• Familiarity and working knowledge of SystemVerilog/Verilog.
• Proven expertise in developing/maintaining timing constraints, timing signoff methodology, timing closure at the block or full-chip level.
• Experience in working with IP vendors for both RTL and hard-macro blocks.
• Good scripting skills in Tcl, Python, or Perl.

Benefits

Base salary range: $160,000 - $195,000 for Staff Level, and $203,000 - $230,000 for Principal Level. Eligible for equity and benefits.

Pay

Base salary determined based on experience and comparable positions.

Schedule

The role is fully on-site and in-person.