Physical Design Engineer Intern, BS - Summer 2027

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Marvell's Physical Design teams span across multiple domains, giving you the opportunity to work on technologies that power next-generation cloud, AI, storage, and networking solutions. Some teams focus their design work on supporting architecture to GDSII implementation of ASIC and processor designs. Other teams focus on timing analysis for future designs of our next-gen high-performance data center chips in a leading-edge CMOS process technology. Across all groups, you'll collaborate with your direct team and cross-functional partners, working through technical design challenges to ensure we meet the performance, power, and area requirements of an active design.

What You Can Expect

• Perform synthesis, floor planning, place and route, clock insertion, timing analysis, and timing closure on complex logic blocks using industry standard EDA tools (PrimeTime, Tempus)
• Write scripts in Python, TCL, Perl, and Shell to aid design and development activities
• Utilize problem solving skills to analyze, debug, and implement fixes for design violations using CAD tools
• Collaborate with RTL, Synthesis, and other Design teams to resolve congestion & timing bottlenecks, and ensure that all designs converge & integrate in a timely manner

What We're Looking For

• Currently enrolled in a Bachelor's Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028
• Completed courses focusing on VLSI, digital logic, circuit design, computer architecture, RTL synthesis, Verilog or SystemVerilog, place and route, static timing analysis, digital systems, or microelectronics
• Proficiency in programming & scripting languages like Python, TCL, Perl, and Shell
• Experience working in a Unix type environment
• Experience using tools like Synopsys (PrimeTime), Cadence (Tempus), and Mentor
• Strong analysis, problem solving, and communication skills

Pay

Expected Base Pay Range (USD) 29 - 57, $ per hour. The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.

Benefits

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights for our interns: medical, dental, and vision coverage, perks and discounts, robust mental health resources to prioritize emotional well-being, and paid holidays. Additional compensation may be available for intern PhD candidates. We look forward to sharing more with you during the interview process.