PCB Design Engineer – Altium / Schematic & Layout

Key Responsibilities

• End-to-End Design Ownership: Own the entire PCB lifecycle from initial concept and schematic capture through layout, routing, and manufacturing release.
• Altium Execution: Develop and maintain complex multi-layer PCB layouts and schematics within Altium Designer.
• Signal & Power Integrity: Design multi-layer boards with strict adherence to high-speed signal integrity, robust power distribution networks (PDN), and proper grounding strategies.
• Documentation & NPI: Generate complete fabrication and assembly packages, including Gerber/ODB++ files, BOMs, and manufacturing drawings.
• Cross-Functional Collaboration: Partner closely with hardware, FPGA, firmware, and mechanical engineering teams to seamlessly integrate system constraints.
• Vendor Management: Coordinate directly with fabrication and assembly vendors to proactively resolve DFM/DFT issues.
• Library & Revisions: Manage component selection, maintain the ECAD library, and support board bring-up, debugging, and iterative design revisions.

Required Qualifications

• Altium Mastery: Proven, hands-on experience with advanced PCB layout and schematic capture specifically in Altium Designer.
• Complex Board Design: Experience successfully designing high-layer-count (e.g., 6+ layers), high-density digital and mixed-signal boards.
• Hardware Fundamentals: Deep understanding of stack-up planning, high-speed routing practices, differential pair routing, and impedance control.
• EMI/EMC & Power: Strong grasp of EMI/EMC-aware layout techniques, power distribution, and decoupling strategies.
• Manufacturability: Solid familiarity with PCB fabrication processes, assembly constraints, and DFM guidelines.
• Autonomy: Ability to work independently, manage tight deadlines, and navigate multiple concurrent board revisions.

Nice To Have (Preferred Skills)

• Experience routing high-speed interfaces (e.g., DDR4/5, PCIe, JESD204, Ethernet, or multi-gigabit serial links).
• Experience working with FPGA-based architectures and complex pin-swapping/constraints.
• Familiarity with thermal management strategies and tight mechanical/enclosure integration.
• Exposure to embedded systems architecture and localized DC-DC power supply layouts

Pay

The target base pay for this position is $130,000 - $200,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience.

This is a full time, exempt position, based out of our Saratoga office.

We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that’s your experience – then we’ll be immediately wow-ed.

E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.