MTS Digital Engineering

Responsibilities

• Develop system Verilog RTL IP, logic, and state machines for next generation products
• Perform block level design integration and block level simulations to qualify behavior
• Document design implementation with descriptions and functional diagrams
• Estimate and track power, performance, area (PPA) tradeoffs for RTL designs
• Collaborate with design team members individually and in group meetings to track status and ensure design implementation achieves desired outcomes
• Review and improve Static Timing Analysis (STA) results
• Create Verilog functional models to be used in simulations
• Work closely with verification team to debug verification results
• Support validation team during chip power-on and debug efforts
• Perform design quality checks with CDC/RDC/LINT tools

Qualifications

• BS in Electrical Engineering with 2-3 years experience, or MS in Electrical Engineering or Computer Engineering with 0-1 year of experience
• Coursework: Digital Integrated Circuits, Advanced VLSI Systems, Advanced Computer Architecture, Embedded Systems, Design and Analysis of Algorithms, Fundamentals of Machine Learning
• Background in Digital RTL design including standard LEC, CDC, LINT, DFT, BIST, STA tools
• High aptitude with Verilog and SystemVerilog
• Ability to document design techniques, test, and verification methodology
• Python/perl script development
• Interface with debug, test, product, and reliability engineers for product qualification