ML ASIC Design Engineer

About the role

Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver—The World's Most Experienced Driver™—to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo’s fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states.

Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle’s software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world’s highest performance automotive compute platforms. This role follows a hybrid work schedule and you will report to the Senior Staff Silicon Engineer.

Responsibilities

• Work with researchers and architects to translate high level requirements into hardware features
• Specify and design microarchitectures to deliver world class ML performance
• Perform power, area and performance exploration and optimization of digital ASIC designs
• Design high performance execution units, arithmetic circuits and programmable engines
• Work with verification teams to guarantee functional correctness and performance

Requirements

• BS degree in Computer Engineering or equivalent practical experience
• 5+ years of industry experience with SystemVerilog, ASIC RTL design and microarchitecture
• 3+ years designing and specifying microarchitectures of high performance computing cores (CPU/GPU/NPU)
• Fluency in at least one high level programming language such as Python, C++

Skills

• Experience designing datapath elements of high performance cores (CPU/GPU/NPU)
• Experience working with Chisel (Scala) or other higher-level hardware DSL's
• Working knowledge of machine learning algorithms & how they map to hardware
• Familiarity with Synthesis and power analysis tools
• Experience working with formal tools for datapath verification

Pay

The expected base salary range for this full-time position across US locations is $175,000—$215,000 USD. Actual starting pay will be based on job-related factors, including exact work location, experience, relevant training and education, and skill level.

Benefits

• Discretionary annual bonus program
• Equity incentive plan
• Generous Company benefits program, subject to eligibility requirements