Mixed Signal Logic Design Engineer

About the role

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed-signal IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed-signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.

Responsibilities

• Develop logic design, RTL coding, and simulation for mixed-signal IPs including cell libraries, functional units, IP blocks, and subsystems
• Participate in the definition of architecture and microarchitecture features of the block being designed
• Apply strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation
• Write and optimize mixed-signal logic to meet power, performance, area, and timing goals
• Ensure design integrity for physical implementation
• Review verification plans and implementation to confirm design features are verified correctly
• Resolve and implement corrective measures for failing RTL tests to ensure feature correctness
• Support SoC customers to ensure high-quality integration of the IP block

Qualifications

• Minimum Qualifications: Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 7+ years of industry experience, OR Master's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with 4+ years of industry experience
• In addition, all candidates must have expert-level proficiency in Verilog / SystemVerilog (RTL design), digital logic fundamentals, experience integrating analog IP with digital logic, deep knowledge of RTL-to-GDSII flow, STA, and CDC, familiarity with EDA tools, understanding of timing, power, and performance trade-offs

Preferred Qualifications

• Solid understanding of analog/mixed-signal blocks such as ADCs, DACs, PLLs, and regulators
• DFT as it relates to mixed-signal IPs
• Knowledge of Power Delivery and Power Management systems
• Scripting language experience, including Perl, TCL/Tk, or Python
• Experience with mixed-signal simulation
• Strong debugging skills across analog and digital domains

Pay

$164,470.00 - 232,190.00 USD

Schedule

Shift 1 (United States of America)