Member of Technical Staff, Performance Modeling

About the role

We are seeking a Member of Technical Staff, Functional and Performance Modeling to develop functional and performance models for our scale-up network-attached memory expansion device for AI accelerators. You’ll work as part of our silicon architecture team to perform functional and performance modeling. You should have experience exploring design tradeoffs, validating performance assumptions, and identifying bottlenecks early in the development cycle. This role is well-suited for engineers who enjoy reasoning from first principles, working with incomplete information, and co-exploring the design space as hardware and software evolve together. This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.

The Opportunity Impact: Humanity stands at the dawn of a new industrial revolution driven by AI—one with the potential to redefine how we live on this planet. We are tackling a fundamental challenge at the infrastructure layer: unlocking greater AI capability while dramatically improving efficiency. The work we do here compounds across state-of-the-art AI models, systems, and real-world applications. Timing: Breakthrough technology matters most when it meets the right time. Joining now means real ownership of the company and meaningful influence over product direction and execution. In this early-stage environment, your ideas shape the trajectory of the technology—not just its implementation. You’ll work from first principles, move quickly from insight to execution, and see your contributions directly reflected in what we build. Culture: You’ll work alongside a group of people who care deeply about rigor, clarity, and impact. We value thoughtful disagreement, fast learning, and intellectual fearlessness. This is a place where strong ideas shine, curiosity is encouraged, and growth is a daily practice—not a future promise.

Responsibilities

• Build and maintain system-level (e.g., rack-scale) and chip-level performance models for high-bandwidth data movement between devices operating in the scale-up domain.
• Model workloads from software memory access patterns through data distribution in the network and all the way down to on-device memory channels.
• Work day-to-day with silicon architects, system designers, and workload owners to align performance expectations and constraints.
• Identify performance bottlenecks, scaling limits, and sensitivity points across compute, memory, and interconnects in end-to-end workload settings.
• Clearly communicate modeling assumptions, limitations, and conclusions to both technical and non-specialist stakeholders.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
• 5–10+ years of experience in performance modeling for data movement devices: NICs, memory expansion cards (e.g. CXL), IPU/DPU, NoC.
• Ability to reason across multiple abstraction layers, from architectural details to system-level performance behavior.

Preferred Qualifications

• Prior experience modeling performance for networking protocols with memory semantics.
• Familiarity with shared memory systems and frameworks (e.g. CUDA VMM).
• Familiarity with modern AI/ML technical stack from a workload perspective: large language model inference and sharding, KV caching, serving system (e.g., continuous batching).
• Experience with scale-up and high-bandwidth interconnects (e.g. NVLink or similar technologies).
• Experience with modeling memory subsystems.

Benefits

• Competitive salary with performance-based bonus and early-stage equity grant
• 100% employer-paid Health, Dental, and Vision coverage for you and your dependents
• 401(k) match with immediate vesting, and