Member of Technical Staff, Hardware, Design Verification Engineer

About the role

We are looking for exceptional design verification engineers to ensure our high-performance custom silicon is functionally correct. Starting from architectural and micro-architectural definitions, you will define test bench boundaries and implement test environments across a variety of verification methodologies (simulation, formal, emulation, etc).

Responsibilities

• Verification Strategy & Planning: Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.
• UVM Environment Development: Architect and implement scalable, reusable, and robust test benches using SystemVerilog and UVM (Universal Verification Methodology).
• Constrained-Random Testing: Develop complex sequences and test cases to achieve high functional coverage, ensuring the design handles architectural corner cases and error conditions.
• Coverage-Driven Verification: Define and implement functional coverage models and perform detailed code coverage analysis to quantify verification progress.
• Formal Verification: Leverage formal methods (SVA, Property Checking) where applicable to exhaustively prove the correctness of critical logic.
• Emulation: Use emulation and prototyping platforms like ZeBu/HAPS and Palladium/Protium to perform scaled testing.
• Debug & Analysis: Debug failures using waveform viewers and work closely with RTL designers to resolve functional bugs and architectural non-compliance.
• Automation & Scripting: Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL to streamline the verification cycle.

Requirements

• Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years equivalent industry experience.
• Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).
• Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage.
• Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI).
• Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).

Qualifications

• A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with other engineers.

Preferred Qualifications

• Proficiency SystemVerilog Assertions (SVA) and formal tools (Jasper, VC Formal) to catch temporal logic bugs at the source.
• Understanding of emulation and prototyping solutions and test environments.
• Hands-on experience in post-Silicon bringup, testing, and debug.
• Experience in workflow management, CI/CD, regression definition and visibility, EDA tool configuration and usage, and other infrastructure tasks.

Logistics

• Location: This role is based in Austin, Texas or Palo Alto, California.
• Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD.
• Visa Sponsorship: We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
• Benefits: River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.