Lead SoC Verification Engineer

Responsibilities

• Participate in microarchitecture and design reviews with the designers to better understand the design to help develop a comprehensive DV plan.
• Develop a detailed test bench and plan for the blocks you will be working on and have them reviewed with the design and SW teams.
• DV infrastructure development: Develop scalable test benches and libraries for block level and full chip level verification. Ensure stimulus is portable across verification, emulation and ASIC platforms. Implement test harness to collect various coverage metrics and scoreboards to track progress through regressions.
• Full chip/Block level verification: Develop directed/constrained random/random test cases to fully stress the design, and track discovered bugs.
• System Validation: Work closely with the validation team to use an emulation platform for accelerated verification and SW/HW co development.

Minimum Requirements

• 10+ years of experience in verifying complex ASICs.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• Deep knowledge of industry-standard on-chip interconnect protocols (AMBA CHI/AXI/AXI-S/APB).
• Fluent in System verilog/System-C and UVM.
• Experience verifying designs with multiple power domains using UPF and industry standard tools.
• Proven track record of taking products through first pass Silicon success.

Preferred Qualifications

• Experience with verifying multi-media SOCs.
• Experience working directly with Arm cores and subsystems.
• Experience with modeling and performance validation.
• Exposure to Silicon bring-up.