Lead SoC Design Engineer

Responsibilities

• Microarchitecture: Author detailed microarchitecture documents and drive reviews with software, architecture and verification teams.
• Drive PPA targets: Since we are developing a power-sensitive client product, you will drive performance/power tradeoffs using a data-driven approach to hit aggressive targets.
• Partner with verification team: Participate in reviews of verification and emulation test plans to ensure successful first-pass silicon.
• RTL design: Own RTL coding, Lint/CDC/RDC checks, SDC and VCLP checks, and ensure that the design can be taken through physical design to meet frequency and power requirements.

Minimum Requirements

• 10+ years of experience in developing complex ASICs in advanced nodes.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or equivalent experience.
• Deep knowledge of industry-standard on-chip interconnect protocols (AMBA AXI/AXI-S/APB).
• Experienced with Verilog, SystemVerilog, SystemVerilog Assertions (SVA).
• Proficiency in writing and debugging SDC timing constraints, including multi-cycle paths, false paths, and clock domain crossing constraints.
• Experience with industry-standard ASIC CAD tools for simulation, synthesis, STA, Lint, LEC, CDC, RDC, and power estimation.
• Experience designing with multiple power domains and UPF.

Preferred Qualifications

• Experience with commercial IP integration, ranging from high-speed interfaces (UCIe, DDR) to processing subsystems (CPU, GPU).
• Experience working directly with Arm cores and subsystems.