Lead Performance Modeling Architect, CPU Fabric and LLC
About the role
We are seeking a Lead Performance Modeling Engineer to guide our performance architecture team. You will act as the primary architect for performance models covering next-generation cache hierarchies and I/O coherent interconnects. These models will scale from Automotive to Data Center platforms. You will guide a group of top-performing engineers, converting high-level product requirements into actionable architectural specifications and ensuring our silicon delivers industry-leading performance-per-watt. As a technical lead, you will balance individual technical contributions with team mentorship and multi-functional strategy.
Responsibilities
Defining the long-term vision for our modeling infrastructure, choosing between cycle-accurate, analytical, and stochastic modeling approaches to meet project achievements.
Leading a team of modeling engineers, offering in-depth technical mentorship, conducting code/architecture reviews, and encouraging a culture of rigorous data-driven decision-making.
Acting as the primary liaison between Architecture, RTL Build, and Software teams to resolve complex performance bottlenecks and trade-offs.
Driving the adoption of advanced modeling methodologies (e.g., hybrid emulation/simulation, AI-based performance optimization) to accelerate the build cycle.
Allocating simulation workloads and engineering efforts across several simultaneous projects in the automotive and data center sectors.
Requirements
A Master’s or Ph.D. in Computer Engineering or a related field (or equivalent experience), with 8+ years of experience in high-performance silicon architecture.
Extensive experience managing technical teams or complex projects in the field of performance modeling or computer architecture.
Significant experience building and architecting large-scale simulators in C++ or SystemC, with a focus on modularity and simulation speed.
Significant experience using statistical analysis to validate model accuracy against RTL or silicon and the ability to explain complex performance "cliffs" to executive collaborators.
Qualifications
Full-Stack Performance Experience: You have seen the entire lifecycle of an interconnect—from a whiteboard sketch and C++ model to RTL integration and post-silicon performance tuning.
Standardization Influence: Active participation in industry bodies (e.g., CXL Consortium, Arm ecosystem committees) or a history of published architectural research.
Scalability Expertise: You have a proven record of addressing the outstanding challenges of both low-latency, safety-critical clusters and massive, high-bandwidth mesh networks for cloud-scale deployments.
Critical Thinking: The ability to explain not just how a system works, but also how architectural decisions affect the total cost of ownership for data centers or safety margins in automotive.
Benefits
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 184,000 USD - 287,500 USD for Level 4, and 224,000 USD - 356,500 USD for Level 5. You will also be eligible for equity and benefits.
Pay
The base salary range is 184,000 USD - 356,500 USD.
Schedule
Applications for this job will be accepted at least until May 10, 2026.