Lead Firmware Engineer

What You Will Do

• Map system-level radar requirements and algorithms to efficient FPGA architectures
• Design and implement radar signal processing algorithms in FPGAs (pulse compression, FFT processing, CFAR detection, beamforming, Doppler processing)
• Develop high-throughput, low-latency processing architectures for real-time radar applications
• Implement waveform generation, digital down-conversion, and channelization in FPGA fabric
• Design and optimize pipelined arithmetic units and custom DSP blocks for radar processing
• Interface FPGAs with high-speed ADCs/DACs for radar RF front-end integration
• Validate designs with simulation and verification techniques before hardware integration
• Supporting full life cycle of development and integration of FPGA firmware into hardware systems
• Create and maintain design documentation and test plans
• Deliver technical briefings to a range of internal and external stakeholders
• Coordinate with program managers and technical leads to manage task schedules and budgets
• Provide mentorship to more junior engineers to accelerate their technical and professional development
• Build and maintain high-performing and empowered technical teams

Who You Are

• This position requires the ability to obtain a Top Secret (TS) security clearance
• Bachelor’s degree and at least 7 years of applicable experience, a Master’s degree and at least 5 years of applicable experience, or PhD and at least 2 years of applicable experience
• Experience with FPGA and SoC design entry using Verilog or VHDL
• Experience implementing digital signal processing techniques, filter design, FFT/DFT, fixed-point optimization
• Experience with design flow for Xilinx and/or Intel FPGAs
• Experience with simulation tools such as ModelSim/Questa, VCS, or Incisive
• Demonstrated desire to successfully pursue new challenges, improve and broaden technical skills, seek greater responsibilities, and increase individual value to the organization
• Capable of effectively working in a team environment, often under tight deadlines

Nice to Haves

• Active Security Clearance at the Secret or Top Secret level
• Proficient with Xilinx or Altera SoC platforms
• Proficient with FPGA or ASIC RTL design entry
• Strong background and experience with industry best practices and version control
• Proficient with complex timing closure
• Proficient with complex timing closure
• Experience with Matlab, Python, or C/C++
• Experience with interfacing to high speed DACs and ADCs
• Knowledge of pulse compression, Doppler processing, beamforming, detection algorithms
• Previous experience with RFSoC or Analog Devices ADC/DAC
• Understanding of RF Systems, specifically radar or EW