IP Integration Engineer

About the role

The IP Integration Engineer will be part of a cross-functional design team developing die-to-die and die-to-memory PHY IP. The PHYs are used broadly in APD's custom silicon ASIC products. The successful candidate will be involved in the development of the physical composition (hardening of the PHY) as well as developing methodologies for integrating these into large complex 2.5D and 3.5D ASICs.

Responsibilities

• Develop a detailed understanding of Broadcom's die-to-die PHYs.
• Work with multiple cross-functional teams—analogy design, digital design, physical composition, DFT, timing, and customers—to build PHYs.
• Work with physical composition teams and interposer design teams.
• Work with analog and physical composition teams to optimize the size and power delivery to high IO density PHYs.
• Analyze power integrity (droop, EM, etc…) in various use cases and workloads.
• Develop/write PHY integration documentation for ASIC composition teams.
• Develop a list of Checklist tasks for integration of PHY IP into ASICS.
• Work with IP build teams to complete quality crosschecks to ensure the quality of the PHYs.
• Help support customer and ASIC PHY integration questions.

Requirements

• A Bachelor’s Degree in Electrical or Computer Engineering and 12+ years of related experience; or Masters degree and 10+ years of related experience.
• Understanding of design trade-offs for power, area, and speed in ASIC designs.
• Have an understanding of the ASIC design flow including FET design, RTL, synthesis, timing, floorplanning, power planning, P&R, LVS, DRC, …
• Basic understanding of modern FET architecture including FinFET and Gate All-Around (GAA) topologies.
• Experience with Cadence Innovus or equivalent toolset.
• Experience in reading timing reports from static timing tools such as Tempus or Primetime.
• Strong verbal, written communication.
• Team player that can easily work with different personalities and skill levels.
• Ability to multitask and manage multiple technical issues in parallel.
• Well organized, methodical, and detail oriented.
• Must develop, accurately track, and meet commitments to product or engineering development schedules.

Qualifications

• Experience with the Cadence Virtuoso design environment.
• Experience or coursework with RTL languages (i.e. SystemVerilog, Verilog, VHDL).
• Experience scripting in Skill, TCL, Ruby, Bash, Perl, Python, etc….
• Experience or familiarity with Ansys Redhawk.
• Familiar with timing reports and strategies for fixing violations.
• Experience or familiarity with AI tools such as Chat GPT, Gemini, and/or Cursor.

Skills

• Strong verbal, written communication.
• Team player that can easily work with different personalities and skill levels.
• Ability to multitask and manage multiple technical issues in parallel.
• Well organized, methodical, and detail oriented.

Benefits

Broadcom offers a competitive and comprehensive benefits package including medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Pay

The annual base salary range for this position is USD 129,400.00 To USD 207,000.00

Schedule

The position is located in Fort Collins, CO.