Jobs · Marketing · California

Head of Product Development Engineering

Ethernovia · San Jose, CA · 1 wk ago
HybridMarketing$220k–$280k/yrFull-time

About the Company

Ethernovia is developing the future of Ethernet-based networks to realize the full potential of software-defined and autonomous vehicles, robotics, and other intelligent machines. Founded in 2018, the company's breakthrough data transport and acceleration technology is ushering in a new era of connectivity and capabilities in the vehicle and at the edge, including highly reliable autonomy, over-the-air servicing, and AI-backed applications.

Ethernovia's co-founders are serial technology entrepreneurs with multiple prior successful ventures together. The company is well-funded, backed by leading technology investors, and has secured $154M in total funding to date. Backers include Porsche SE, Qualcomm, AMD, Western Digital, Maverick Silicon, Socratic Partners, Conduit Capital, and CDIB-TEN Capital.

Ethernovia has been recognized in EE Times' prestigious list of the Top 100 Startups for 2025 and has filed 50+ patents. With talented employees on 4 continents, the company is shaping the future of packet processor-centric networking solutions to support real-time sensor, Physical AI, and control data demands of software-defined autonomy across vehicles, robots, and intelligent machines.

About the Role

The Head of Product Development Engineering will be responsible for taking Ethernovia's products from NPI (New Product Introduction) to HVM (High-Volume Manufacturing). This position requires a leader who is hands-on with semiconductor product development, bridging the gap between world-class networking chip designs and high-volume, automotive-grade silicon manufacturing. The position is based in San Jose, CA.

Responsibilities

  • End-to-end product test and hardware ownership from pre-silicon to post-silicon, collaborating with Architecture, Design, SW/FW, DFT, System, Test (ATE/BI/SLT), and Q&R teams.
  • Execute NPI bring-up for high-speed Ethernet switch and PHY products, ensuring signal integrity and power/performance standards are maintained at scale.
  • Drive the execution of the manufacturing flow from wafer starts to sample delivery.
  • Own test strategy across wafer test, final test, and system-level test.
  • Own characterization, ATE to system correlation, productization, and manufacturing specs and margins (transistor to PMIC, part-to-part, aging, and GRR).
  • Own yield improvement across process/package/test, drive test time and test cost reduction while meeting automotive quality requirements.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering or a related technical field.
  • 12+ years of experience in fabless semiconductor operations, specifically for complex, high-performance SOCs or networking ICs.
  • Direct experience with ATE and SLT testing, characterization, ATE to system correlation, productization, and silicon/package qualification.
  • Direct experience working with foundries, assembly houses, test houses, and OSATs in developing high-volume products from NPI through HVM.
  • Expertise with iJTAG, Scan, MBIST, Sensor, SerDes, LSIO/HSIO testing on ATE, bare-metal, functional DVFS, and benchmark testing at SLT and security fusing.
  • Experience productizing high-speed communications chips using ATE and system characterization and correlation data, balancing PPY (power/performance/yield).
  • Experience navigating the automotive electronics ecosystem, including IATF 16949, ISO 26262, safe launch, and PPAP (Production Part Approval Process).
  • Experience working in a fast-paced startup environment building cutting-edge products.

Skills

  • Understanding of high-bandwidth data-path products (Ethernet, Switching, or high-speed SerDes).
  • Expert-level experience with yield management systems, data analysis, scripting tools, and statistical data analysis using JMP.
  • Understanding of the product life cycle from concept to end-of-life and leading pre-silicon review and readiness to enable seamless post-silicon bring-up.

Preferred Qualifications

  • Familiarity with the latest FinFET process node and QFN, LGA/BGA assembly processes for automotive products.
  • Experience delivering high-speed SerDes products to Tier-1 automotive OEMs.
  • Experience managing contractors and leadership experience.

Benefits

  • Pre-IPO stock options.
  • Cutting-edge technology exposure and career growth opportunities.
  • World-class team collaboration.
  • Competitive base salary and flexible hours.
  • Medical, dental, and vision insurance for employees.

Pay

The actual offered base salary for U.S. locations will vary depending on factors such as work location, individual qualifications, specializations, years of experience, skills, job-related knowledge, and internal equity. The annual salary range for this position is $220,000 - $280,000. The compensation package will also include incentive compensation in the form of pre-IPO ISO options, in addition to base salary and a full range of medical and other benefits.

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