HBM SoC RTL Design Engineer

About the role

As a SoC Design Engineer, you will be part of the Heterogeneous Integration Group (HIG), contributing to the design, development, and integration of next-generation HBM SoC logic die. You will work closely with architecture, verification, physical design, firmware, and product teams to implement robust, high-performance SoC solutions that meet ambitious power, performance, area, and schedule targets. You will also work to enable and integrate AI-driven tools and AI-enabled workflows into the team's methodologies.

Responsibilities

• Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Collaborate with SoC architects to translate architectural and micro-architectural specifications into high-quality RTL implementations.
• Participate in SoC-level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues.
• Contribute to design documentation, block specifications, and design reviews.
• Collaborate multi-functionally with Product Engineering, Test, Probe, Process Integration, and Manufacturing to ensure robust and manufacturable builds.

Requirements

• Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field, with a minimum of 3 years of experience in a related field.
• Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
• Experience with the RTL-to-GDS flow, including synthesis, static timing analysis, and develop sign-off considerations.
• Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
• Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).

Preferred Qualifications

• Experience with HBM, DRAM, or memory-centric SoC designs.
• Familiarity with high-speed interfaces, clocking strategies, reset architectures, and power management concepts.
• Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
• Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).
• Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.

Pay

The US base salary range for this full-time position is $121,000.00 - $247,000.00 a year. Additional compensation may include benefits, bonuses, and equity. Salary ranges are determined by role, level, and location. Individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure, and relevant education or training.

Benefits

• A choice of medical, dental, and vision plans.
• Income protection programs if unable to work due to illness or injury, and paid family leave.
• A robust paid time-off program and paid holidays.

For additional information regarding the benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.