Hardware / Software CoDesign Engineer - 3P

OpenAI’s Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team builds next-generation AI-native silicon, working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI’s supercomputing infrastructure, the team creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI.

About the role

As an Engineer on our hardware optimization and co-design team, you will co-design future hardware from different vendors for programmability and performance. You will collaborate with kernel, compiler, and machine learning engineers to understand their needs related to ML techniques, algorithms, numerical approximations, programming expressivity, and compiler optimizations. You will evangelize these constraints with vendors to influence future hardware architectures for efficient training and inference on OpenAI’s models.

This role is based in San Francisco, CA. We use a hybrid work model of 3 days in the office per week and offer relocation assistance to new employees.

Responsibilities

• Co-design future hardware for programmability and performance with hardware vendors
• Assist hardware vendors in developing optimal kernels and add support for them in our compiler
• Develop performance estimates for critical kernels across different hardware configurations and drive decisions on compute core and memory hierarchy features
• Build system performance models at different abstraction levels and analyze them to inform decisions on scale-up, scale-out, and front-end networking
• Work with machine learning engineers, kernel engineers, and compiler developers to understand their vision and needs from high-performance accelerators
• Manage communication and coordination with internal and external partners
• Influence the roadmap of hardware partners to optimize them for OpenAI’s workloads
• Evaluate potential partners’ accelerators and platforms
• As the scope of the role and team grows, understand and influence roadmaps for hardware partners regarding datacenter networks, racks, and buildings

Requirements

• 4+ years of industry experience, including experience harnessing compute at scale and optimizing ML platform code to run efficiently on target hardware
• Strong experience in software/hardware co-design
• Deep understanding of GPU and/or other AI accelerators
• Experience with CUDA, Triton, or a related accelerator programming language
• Experience driving Machine Learning accuracy with low-precision formats
• Experience with system performance modeling and analysis to optimize ML model deployment
• Strong coding skills in C/C++ and Python
• Familiarity with the fundamentals of deep learning computing and chip architecture/microarchitecture
• Able to actively collaborate with ML engineers, kernel writers, compiler developers, system engineers, chip architects, and microarchitects

Preferred Skills

• PhD in Computer Science and Engineering with a specialization in Computer Architecture, Parallel Computing, Compilers, or other Systems
• Strong understanding of LLMs and challenges related to their training and inference

Pay

Compensation range: $342K - $555K