Hardware/ Software Co-Design Engineer

About the role

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications.

Responsibilities

As a Hardware/Software Co-Design Engineer, you will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus on high-throughput, low-power digital signal processors (DSP) and general-purpose hardware accelerators for state-of-the-art brain-computer interfaces.

• Micro-architecture design and RTL implementation of:
  • Low-power digital signal processors
  • Low-power general-purpose hardware accelerators
  • Low-power graphics processing units
  • Low-power radio MAC/PHY
  • Low-power serial link MAC/PHY
• Design and optimization of hardware/software interface with firmware engineers
• Application-specific architecture optimization including:
  • Complex system modeling for energy and performance benchmarks
  • Workload analysis and modeling
  • Energy/performance profiling and analysis
  • Leveraging architecture-level design trade-offs with process technology and workload type
  • Balancing cost and performance under manufacturing process variation
• Collaboration on silicon bring-up tests with verification engineers

Requirements

• Bachelor of Science (B.S.) degree in Electrical Engineering and/or Computer Science or a related field, or equivalent experience
• Evidence of exceptional ability in electrical engineering, computer science, or computer engineering
• Experience designing and implementing embedded software in C or Rust
• Expertise in SystemVerilog, C/C++, Python
• Experience designing and implementing emulation models, transactors, and test environments to replicate hardware behavior
• Experience working on complex digital systems from architecture, microarchitecture, and RTL, using industry standard tools
• Experience in designing digital signal processing pipelines, from algorithm to RTL

Preferred Qualifications

• Experience in architecture optimization with process technology customization
• Experience in the verification of complex digital systems, using industry standard tools
• Experience in the physical design of complex digital systems, using industry standard tools
• Experience testing and debugging digital system-on-a-chips
• Functional modeling experience and logic verification with SystemVerilog, SystemC/C++
• Experience automating tool flows
• Experience in processor instruction set architecture design
• Experience in compiler back-end design and customization

Pay

Base Salary Range: $151,000 USD - $261,000 USD. In addition to base salary, Neuralink offers equity compensation in the form of Restricted Stock Units (RSU) for all full-time employees.

Benefits

• Full-time employees are eligible for the following benefits:
  • Excellent medical, dental, and vision insurance through a PPO plan
  • Paid holidays
  • Commuter benefits
  • Meals provided
  • Equity (RSUs)
  • 401(k) plan (after 1,000 hours for interns)
  • Parental leave
  • Flexible time off
• Opportunity to change the world and work with some of the smartest and most talented experts from different fields
• Growth potential; we rapidly advance team members who have an outsized impact