Hardware Security Architect

Job Responsibilities

• Define SoC hardware security architecture and requirements, including HSM specification, secure boot/RoT concepts, and cryptographic IP integration strategies.
• Translate security features into high-level HW/SW specifications and derive HW requirements to design a product.
• Lead threat modeling, risk assessments, and vulnerability analysis; translate into architectural mitigations and design constraints.
• Architect HW/SW security boundaries and co-design flows for secure boot, firmware services, drivers, and runtime protection.
• Define secure key storage/provisioning (eFUSE/OTP) and security-aware DFT/TEST strategies balancing coverage and attack resistance.
• Collaborate with architecture, RTL, verification, DFT, PD, and software teams to embed security into implementation and validation flows.
• Ensure compliance with cybersecurity standards (ISO 21434), optimize for PPA trade-offs, and drive system-level security validation.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronic/Computer Engineering or a related field.
• 10–15+ years of experience in SoC or MCU design with a strong focus on hardware security architecture and HW/SW interactions.
• Strong understanding of SoC architecture, AMBA/AXI-class interconnects, memory subsystems, and how security policies are enforced across HW/SW boundaries.
• Proven experience with threat modeling, risk assessment, security validation, and vulnerability analysis for SoC-based systems.
• Hands-on background with RTL design, synthesis concepts, and EDA flows sufficient to review and guide secure implementation (even if not the primary RTL owner).
• Excellent written and verbal communication skills for specifications, reviews, and stakeholder alignment.