Hardware Engineering Technical Leader (hybrid) - 2014270

Responsibilities

• Define comprehensive validation strategies, including the planning and execution of Test Readiness Reviews (TRRs).
• Lead the root cause analysis of complex silicon failures, driving solutions to ensure product quality.
• Design and implement sophisticated test processes and methodologies, including hardware-software integration, parameter optimization, and advanced equipment metrology.
• Collaborate closely with Design, Process Development, and Manufacturing teams to identify and implement solutions for yield optimization and product performance improvement.
• Contribute to pathfinding efforts in advanced packaging technologies, applying expertise in areas such as SystemVerilog, UVM, and emulation platforms to develop robust test solutions.
• Mentor and guide a team of staff engineers, fostering a culture of technical excellence and innovation.
• Provide technical direction for test engineering activities and collaborate with vendors to develop and qualify enabling test technologies and equipment.
• Work effectively with cross-functional teams, including design, product engineering, and manufacturing, to ensure seamless product development and ramp-up.

Requirements

• Bachelor's or Master's degree in Electrical Engineering.
• Proven experience in semiconductor test engineering, with a strong track record of leading complex test development and validation efforts.
• Deep understanding of silicon validation methodologies, including test planning, execution, and failure analysis, including complex SerDes.
• Expertise in designing sophisticated test processes, hardware-software integration, parameter optimization, and equipment metrology.
• Experience with yield enhancement initiatives and working closely with design, process, and manufacturing teams.
• Familiarity with advanced packaging technologies and their associated test challenges.
• Proficiency in test development languages and methodologies such as SystemVerilog, UVM, and/or C/C++.
• Experience with Advanced technology nodes in areas of testing, yield, silicon debug at probe, final test, and system level test.
• Demonstrated technical leadership experience, including mentoring junior engineers and guiding technical direction.
• Excellent problem-solving, analytical, and communication skills.
• Ability to collaborate effectively in a fast-paced, cross-functional environment.

Qualifications

• Minimum qualifications include a Bachelor's or Master's degree in Electrical Engineering.
• Proven experience in semiconductor test engineering, with a strong track record of leading complex test development and validation efforts.
• Deep understanding of silicon validation methodologies, including test planning, execution, and failure analysis, including complex SerDes.
• Expertise in designing sophisticated test processes, hardware-software integration, parameter optimization, and equipment metrology.
• Experience with yield enhancement initiatives and working closely with design, process, and manufacturing teams.
• Familiarity with advanced packaging technologies and their associated test challenges.
• Proficiency in test development languages and methodologies such as SystemVerilog, UVM, and/or C/C++.
• Experience with Advanced technology nodes in areas of testing, yield, silicon debug at probe, final test, and system level test.
• Demonstrated technical leadership experience, including mentoring junior engineers and guiding technical direction.
• Excellent problem-solving, analytical, and communication skills.
• Ability to collaborate effectively in a fast-paced, cross-functional environment.

Skills

• Strong technical background in semiconductor test engineering.
• Experience with advanced test technologies and methodologies.
• Collaborative and leadership skills.
• Problem-solving and analytical skills.
• Effective communication skills.

Benefits

• Medical, dental, and vision insurance.
• A 401(k) plan with a Cisco matching contribution.
• Paid parental leave.
• Short and long-term disability coverage.
• Basic life insurance.
• Volunteer time off.
• Flexible vacation time off.
• Performance-based incentive pay for quota-based sales roles.

Pay

• The starting salary range for this position is $191,400.00 to $281,400.00.

Schedule

• This position requires work activity to be onsite a number of days (TBD) each week in San Jose CA office.