Hardware Engineer (Space)
About the role
In this role you will be in charge of hardware design of high-speed digital boards for space applications. Your contributions will include defining FPGA architecture, SoC integration, schematic capture, and mixed-signal circuit design including ADC/DAC interfaces. You will be part of a multidisciplinary engineering team through the full hardware development lifecycle from requirements and concept through design, verification, and flight qualification.
Responsibilities
- Define and drive FPGA architecture and SoC integration across the hardware platform
- Design high-speed digital interfaces including DDR4, SERDES, UART, and SPI
- Perform HyperLynx power/signal integrity analysis and implement corrective design changes
- Conduct worst case analysis (WCA) to verify design margins across operating conditions, voltage, and temperature
- Design mixed-signal circuits including ADC and DAC interface architectures
- Collaborate with firmware, software, and systems engineers for hardware/firmware co-design and integration
- Support board bring-up, integration, and debug in the laboratory
- Generate and maintain design documentation including schematics, BOMs, design review packages, and interface control documents
- Owning and driving technical issues to resolution
- Works autonomously to solve well-defined problems
Requirements
- Bachelor Degree in Electrical Engineering or a related field
- 2+ years of hardware engineering experience with high-speed digital board design
- Experience with schematic capture tools (e.g., Mentor Xpedition, Cadence)
- Demonstrated experience working in a multidisciplinary engineering team
- Proven troubleshooting and debug skills for complex high-speed digital hardware
- Good oral and written communications skills
What Will Help You On The Job
- MSEE degree preferred
- Knowledge of power integrity analysis tools
- Knowledge of PCB layout tools and high-speed layout design rules
- Knowledge of thermal and mechanical design constraints for space hardware
- Knowledge of high-speed interface design: DDR4, SERDES, UART, and SPI
- Familiarity with FPGA architecture definition and SoC integration experience
- Familiarity with GitHub
- Familiarity with CI/CD practices
- Familiarity with AI Agents (Claude Code, Copilot, etc.)
Pay
Salary range $104,500.00 - $164,500.00 / annually. For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $129,000.00- $194,000.00/ annually
Benefits
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat’s comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
EEO Statement
Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this on-line application, please click here.