GPU Performance Engineer | Experienced Hire
Susquehanna International Group · Bala-Cynwyd, PA · 1 wk ago
On-siteEngineeringFull-time
About the role
This role is focused on workloads where off-the-shelf runtimes and vendor libraries do not fully exploit the structure of the model, and where custom kernels, memory layouts, and execution strategies can deliver meaningful gains.
Responsibilities
- Design, implement, and optimize custom CUDA kernels for latency-critical inference workloads
- Develop fine-grained GPU implementations tailored to specific model structures
- Analyze quantitative research models and computational bottlenecks to identify opportunities for parallelization and hardware-efficient execution
- Collaborate directly with quantitative researchers to translate mathematical models into high-performance compute pipelines
- Optimize end-to-end inference performance through kernel tuning, memory-layout design, execution strategy, I/O optimization, and precision tradeoffs
- Profile and benchmark GPU performance
- Improve latency and throughput in production inference systems
- Contribute to GPU architecture decisions and performance best practices
Requirements
Strong proficiency in writing and optimizing CUDA kernels
Solid programming experience in C/C++ (preferred)
Deep understanding of GPU architecture, including memory hierarchy, SIMT execution, occupancy, and latency/throughput tradeoffs
Ability to reason about numerical stability, precision, performance tradeoffs, and how model design choices affect hardware efficiency
Strong problem-solving skills and comfort working with low-level systems
Preferred Qualifications
- PhD in mathematics, physics, computer science, engineering, or related quantitative field
- Strong background in linear algebra, probability, numerical methods, or scientific computing
- Experience working with quantitative research teams or financial models
- Demonstrated ability to improve real-world inference performance beyond baseline framework or library implementations
- Familiarity with PTX-level behavior, tensor core utilization, or architecture-specific tuning
- Exposure to ONNX Runtime, TensorRT, Triton, TVM, or similar systems
- Experience with neural networks, tree-based models (e.g., LightGBM), state space models (e.g., Mamba architectures), and experience with kernel fusion, custom operators, model compilation, or graph-level optimization