FPGA Verification Engineer

About the role

Location: Santa Clara, CA — 100% onsite, Monday through Friday. Duration: 12+ months.

We are seeking an experienced FPGA Verification Engineer with deep expertise in FPGA design principles, SystemVerilog, and UVM methodology. You will work with industry-standard verification tools, perform code and functional coverage analysis, and collaborate closely with design and verification teams to ensure high-quality FPGA implementations.

Responsibilities

• Apply strong understanding of FPGA design principles and architectures
• Develop and execute verification plans using SystemVerilog and UVM methodology
• Work with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS)
• Perform code coverage and functional coverage analysis
• Debug complex verification issues and drive root-cause resolution
• Communicate effectively and collaborate across design, verification, and project teams

Requirements

• Bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field
• Proven experience in FPGA verification
• Experience with scripting languages (e.g., Python, Perl)
• Familiarity with hardware description languages (e.g., VHDL, Verilog)

Skills

• 8+ years of FPGA experience
• 5+ years of UVM verification methodology experience
• 5+ years of SystemVerilog experience

Schedule

Full-time, onsite in Santa Clara, CA — Monday through Friday, day shift.