FPGA Engineer

We are seeking an FPGA Design Engineer with over 8 years of experience to develop architecture, implementation, and verification for complex, high-speed FPGA solutions. The ideal candidate will have expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5.

About the role

This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will support the development of a cryptography platform, collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.

Responsibilities

• Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.
• Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.
• Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure.
• Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.
• Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.
• Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.
• Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

Requirements

• 8+ years of experience developing architecture, implementation, and verification for complex, high-speed FPGA solutions.
• Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
• Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.
• Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
• Proficiency in FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
• Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
• Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422).
• Experience with System-on-Chip (SoC) technologies.
• Active DoD Secret Clearance.

Work Environment

This position requires 100% onsite work due to the nature of the projects. The schedule follows a 9/80 arrangement, allowing every other Friday off.

Pay

The pay range for this position is $75.00 - $90.00 per hour. Individual compensation offered within this range will depend on qualifications, skills, relevant experience, job knowledge, geographic location, internal equity, and other pertinent job-related factors.

Benefits

Eligibility requirements apply to some benefits and may depend on job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include:

• Medical, dental, and vision insurance.
• Critical Illness, Accident, and Hospital coverage.
• 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available.
• Life Insurance (Voluntary Life & AD&D for the employee and dependents).
• Short- and long-term disability.
• Health Spending Account (HSA).
• Transportation benefits.
• Employee Assistance Program.
• Time Off/Leave (PTO, Vacation, or Sick Leave).

Schedule

This is a Contract to Hire position based in Melbourne, FL.