FPGA Design Engineer

Responsibilities

• Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.
• Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.
• Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.
• Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.
• Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.
• Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

Requirements

• 8+ years of experience to develop architecture, implementation, and verification for complex, high-speed FPGA solutions.
• Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
• Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.
• Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
• Proficiency in FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
• Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
• Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422).

Qualifications

• Active DoD Secret Clearance required.
• Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero).
• Familiarity with Universal Verification Methodology (UVM).
• Familiarity with Microsemi Libero and Lattus Diamond.
• Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation.
• Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers.
• Support JTAG Boundary scan design and testing.
• Strong oral and written communication skills, with ability to document and present technical work clearly.
• Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).
• Understanding of formal verification processes and compliance standards.