Fall 2026 Co-Op - Digital Design Engineer

Responsibilities

• Design and implement RTL modules using Verilog for DSP and data conversion ICs.
• Perform logic simulation, functional verification, and synthesis in a mixed-signal environment.
• Collaborate with the design team on integration and system-level verification.
• Support behavioral modeling of analog and mixed-signal circuits.
• Assist with test vector generation and lab test development.

Requirements

• Currently pursuing a MS or PhD in Electrical Engineering or a related field.
• Strong understanding of Digital Signal Processing (DSP) concepts.
• Proficiency in Verilog and Synopsys-based design flows.
• Experience with Matlab for algorithm development and analysis.
• Familiarity with PWM techniques, transistor-level simulators, and place-and-route tools.

Qualifications

• Based within commutable distance of the work location listed on the job posting, or willing to relocate prior to beginning their internship with Cirrus Logic.
• Must be able to access technical data without a requirement for an export license.

Benefits

• Hands-on opportunity to work in a collaborative, innovation-driven environment.
• Your contributions will directly impact real-world products.
• Full-time schedule during the Fall 2026 semester.

Schedule

2+ day in-office work schedule but interns should expect to be in the office more often, up to 5 days per week, based on business needs and team preference.

Pay

Details on pay are not specified in the job posting.