Embedded Software Development Engineer (R&D Engineer 2/3)

About the Role

This position will be filled at either the Embedded Software Development Engineer R&D 2 or 3 level, depending on the skills of the selected candidate. Additional responsibilities will be assigned if the candidate is hired at the higher level.

The Automation, Robotics, and Control Group (E-3) is seeking an experienced FPGA/Embedded Software Development Engineer to join the Embedded Systems for Weapons Analysis (ESWA) team at Los Alamos National Laboratory. ESWA is a multidisciplinary team specializing in high-speed data acquisition systems, with expertise in systems engineering, embedded systems for data acquisition, and mechanical design of complex miniaturized systems for harsh conditions. The ESWA team supports LANL's flight programs for verification, reliability surveillance, and system development.

As part of the ESWA team, you will contribute to joint-scope objectives for LANL systems by providing critical data and performance metrics for flight-tested assets. In E-3, innovation is driven by employees with diverse skills and experiences. You will have opportunities to work across different programs, expanding your skills and interests.

Responsibilities

R&D Engineer 2 ($106,400 - $176,000)

• Identify and apply digital design methodologies suitable for deployment in harsh flight environments.
• Work closely with other engineers and scientists to develop, deploy, and test firmware and software for on-board data processing and analysis.

R&D Engineer 3 ($122,300 - $206,300)

• All responsibilities of R&D Engineer 2.
• Serve as a technical leader with advanced skills in digital hardware design.
• Provide in-depth evaluation of design variables and technical decision-making for project leadership.
• Build communication skills through leadership opportunities, collaborations, and mentoring early career staff.

Requirements

Minimum Job Requirements

Technical Knowledge

• FPGA Development: Hands-on experience with FPGA design, development, and testing, including familiarity with platforms like Xilinx, Altera/Intel, or Lattice. Ability to translate system-level requirements to FPGA requirements, perform design, modeling, simulation, and implementation. Experience with tools like Xilinx Vivado, XSIM, Intel Quartus, ModelSim, or other synthesis and simulation software. Ability to debug, simulate, and validate FPGA implementations using logic analyzers, oscilloscopes, or integrated debugging tools like Xilinx ILA/ChipScope/SignalTap.
• Hardware Description Languages (HDL): Solid knowledge and experience in VHDL and/or Verilog for FPGA design and simulation. Experience designing and simulating digital circuits, creating placement and timing constraints, performing synthesis, place and route, and on-board device configuration.
• Digital Logic Design: Proficiency in designing combinational and sequential logic, state machines, and data path architectures.
• Digital Signal Processing (DSP): Familiarity with common DSP algorithms and techniques.
• Communication Protocols: Proficiency in designing and implementing interfaces for high-speed communication protocols such as SPI, I2C, UART, SpW, etc.
• Problem-Solving: Strong analytical skills and attention to detail for troubleshooting and optimizing FPGA designs. Experience debugging and troubleshooting circuits and prototypes.

Collaboration

• Demonstrated ability to be an effective member of a multidisciplinary team.
• Experience providing technical direction and/or guidance to junior staff and peers.
• Strong organization skills to accomplish technical tasks while working independently, with occasional oversight on specific objectives and complex problems.
• Ability to collaborate with cross-functional teams to optimize designs for performance, cost-effectiveness, and manufacturability.
• Demonstrated ability to clearly communicate technical material verbally, in writing, and in presentations.

Additional Requirements for R&D Engineer 3

• Participate as a technical leader with recognized, advanced skills in digital hardware design.
• Provide in-depth evaluation of design variables and technical decision-making for project leadership.
• Build communication skills through leadership opportunities, collaborations, and mentoring early career staff.

Education/Experience

• R&D Engineer 2: Bachelor's Degree in Engineering from an accredited institution and 4 years of related experience; or an equivalent combination of education and experience.
• R&D Engineer 3: Master's Degree in Engineering from an accredited institution and 6 years of related experience; or an equivalent combination of education and experience. A Ph.D. may be preferred at this level.

Qualifications

• Active Q Clearance or equivalent DoD clearance.
• Experience with Advanced Microcontroller Bus Architecture (AMBA), Advanced eXtensible Interface (AXI), and Advanced Peripheral Bus (APB).
• Experience with MATLAB System Generator for DSP with HDL Coder.
• Experience with High-Level Synthesis (HLS) tools like Xilinx HLS or Intel HLS for converting C/C++ to FPGA implementations.
• Experience with advanced, high-performance FPGA families/architectures such as Xilinx UltraScale+ or Intel Stratix.
• Experience implementing soft or hard processor cores in FPGAs (e.g., MicroBlaze, Nios II) and their integration with custom logic.
• Familiarity with partitioning functions between hardware and software, including experience with system-on-chip (SoC) FPGA solutions.
• Proficient experience with scripting tools such as Python, Tcl, or Perl to automate FPGA design, synthesis, and testing processes.
• Familiarity with advanced verification techniques using SystemVerilog and Universal Verification Methodology (UVM).
• Experience working with real-time operating systems (RTOS) or low-latency designs in FPGA environments.
• HW/SW Codesign using System-on-Chip (SoCs) devices with embedded ARM or Microblaze processors.
• Experience or knowledge of best practices for maintaining signal integrity in mixed analog/digital designs from circuit design to PCB layout.
• Experience with FPGA and digital design tools such as Microchip (Microsemi/Actel), AMD (Xilinx), Lattice, Intel (Altera), Siemens (ModelSim), Synopsys (Synplicity), Aldec.

Work Location

The work location for this position is onsite in Los Alamos, NM. All work locations are at the discretion of management.

Benefits

• PPO or High Deductible medical insurance with a large nationwide network.
• Dental and vision insurance.
• Free basic life and disability insurance.
• Paid childbirth and parental leave.
• Award-winning 401(k) (6% matching plus 3.5% annually).
• Learning opportunities and tuition assistance.
• Flexible schedules and time off (PTO and holidays).
• Onsite gyms and wellness programs.
• Extensive relocation packages (outside a 50-mile radius).