Embedded AI Tooling Engineer

About the role

Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™. Learn more at www.analog.com and on LinkedIn and Twitter (X).

Responsibilities

• Work with team members to design, implement, and release novel AI model deployment tools and infrastructure for heterogeneous computer architectures such as DSPs, NPUs, and CPUs as part of a larger SoC.
• Build end-to-end workflows spanning model development, optimization, hardware-specific architecture, and deployment to ADI's embedded platforms—enabling developers to seamlessly move from model conception to production on resource-constrained devices.
• Develop tools and infrastructure for hardware-aware model design, including architecture mapping techniques that adapt neural network structures to leverage specific hardware capabilities (DSP operations, NPU features, mixed-precision computation).
• Design and implement model compilation and optimization pipelines that enable seamless quantization, pruning, layer fusion, and hardware-specific code generation for ADI's embedded hardware platforms.
• Explore and prototype agentic AI workflows that leverage autonomous agents for automated model-hardware co-optimization, intelligent architecture search, and adaptive deployment strategies.
• Become a thought leader in developing a company-wide strategy around production-quality embedded AI deployment infrastructure and hardware-aware model development tooling.

Requirements

• Strong embedded systems and computer architecture experience (bare-metal, RTOS, or embedded Linux).
• Expertise in end-to-end AI/ML model development, from training through optimization and deployment on embedded platforms.
• Experience with hardware-aware neural architecture design and model optimization techniques tailored to specific processor architectures.
• Proficiency in C, C++, Python, with experience in firmware and low-level software development.
• Deep understanding of neural network quantization, pruning, knowledge distillation, and optimization techniques for resource-constrained devices.
• Knowledge of neural network accelerators (NPUs, DSPs) and efficient execution of neural networks on heterogeneous hardware.
• Familiarity with AI/ML frameworks (TensorFlow, PyTorch) and deployment tools (TensorFlow Lite, ONNX Runtime, TVM, etc.).
• Experience with build systems (CMake, Make, Ninja), CI/CD pipelines, and infrastructure automation.
• Background in ML algorithms (CNN, DNN, Transformer architectures) and their embedded implementation.
• Experience with developer tooling (debuggers, profilers, SDKs, system configuration tools).

Qualifications

• Experience with hardware-software co-design and custom operator development for specialized hardware.
• Knowledge of neural architecture search (NAS) and automated model optimization techniques.
• Background in digital signal processing (DSP) and algorithm implementation experience.
• Experience with agentic AI systems, multi-agent frameworks, or autonomous optimization workflows.
• Experience with edge AI frameworks and deployment tools (TensorFlow Lite Micro, ONNX, Apache TVM, MLIR).
• Understanding of compiler optimizations and code generation for embedded AI accelerators.
• Experience with FPGA development including design, synthesis, simulation, and verification.
• Experience with Zephyr RTOS and open-source RTOS ecosystems.
• Experience contributing to and working with open-source ecosystems.
• Understanding of heterogeneous architectures (ARM, RISC-V, DSPs, custom SoCs).

Skills

• Experience with hardware-aware neural architecture design and model optimization techniques tailored to specific processor architectures.
• Knowledge of neural network accelerators (NPUs, DSPs) and efficient execution of neural networks on heterogeneous hardware.
• Experience with agentic AI systems, multi-agent frameworks, or autonomous optimization workflows.
• Understanding of compiler optimizations and code generation for embedded AI accelerators.
• Experience with FPGA development including design, synthesis, simulation, and verification.
• Experience with Zephyr RTOS and open-source RTOS ecosystems.
• Experience contributing to and working with open-source ecosystems.
• Understanding of heterogeneous architectures (ARM, RISC-V, DSPs, custom SoCs).

Benefits

• Medical, vision, and dental coverage.
• 401(k) plan.
• Paid vacation, holidays, and sick time.

Pay

$110,385 to $151,808

Schedule

1st Shift/Days